Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 12/04/2023
Public
Document Table of Contents
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7.2. Design Flow Using the In-System Sources and Probes Editor

The In-System Sources and Probes Editor supports an RTL flow. Signals that you want to view in the In-System Sources and Probes editor are connected to an instance of the In-System Sources and Probes IP core.
After you compile the design, you can control each instance via the In-System Sources and Probes Editor pane or via a Tcl interface.
Figure 106. FPGA Design Flow Using the In-System Sources and Probes Editor