F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 4/01/2024
Document Table of Contents

1.5. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel device, follow these steps:
  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, navigate to the Quartus® Prime project directory eth_f_0_example_design/hardware_test_design/.
  3. Open the Quartus® Prime project:
    quartus eth_f_hw.qpf &
  4. On the Processing menu, click Start Compilation.
  5. After successful compilation, a .sof file is available in <design_example_directory>/hardware_test_design/output_files.
    • Connect the Agilex 7 I-Series Transceiver-SoC Development Kit to the host computer.
    • Launch the Clock Controller application, which is part of the development kit.
      Figure 9. Clock Controller
      Set new frequencies for the design example as following:
      • Si5394 (U118), OUT3: Set to the value of i_refclk2pll 2 as 156.25MHz.
  6. On the Tools menu, click Programmer.
  7. In the Programmer, click Hardware Setup.
  8. Select a programming device.
  9. Select and add the Development Kit to which your Quartus® Prime Pro Edition session can connect.
  10. Ensure that Mode is set to JTAG.
  11. Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
  12. In the row with your .sof, check the Program/Configure box for the .sof file.
  13. Click Start.
Note: If the System PLL fails to lock when the i_refclk2pll frequency is greater than 156.25MHz, please refer to the steps specified in Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies? to resolve the issue.
2 The Clock Control GUI application cannot drive all the frequencies.