F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 4/01/2024
Document Table of Contents

6.1. Features

  • Supports two instantiations of F-Tile Ethernet Intel FPGA Hard IP and F-Tile Auto-Negotiation and Link Training for Ethernet on two separate tiles.
  • Two instantiations of F-Tile Reference and System PLL Clocks Intel® FPGA IP based on Ethernet configuration