F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 4/01/2024
Document Table of Contents

6.2. Functional Description

Figure 18.  F-Tile Ethernet Intel FPGA Hard IP Simulation Design Example Block Diagram with Enabled Auto-Negotiation and Link TrainingThe diagram depicts the FGT PMA option.
The F-Tile Ethernet Intel FPGA Hard IP design example includes the following components:
  • F-Tile Ethernet Intel FPGA Hard IP : Generated two separate instances of IP core.
  • : Generated two instances of IP core when auto-negotiation and link training is enabled.
    Note: B0 FHT multi-lane designs support bonding by default in F-tile AN/LT IP, and nonbonded FHT multi-lane designs are not supported.
  • : Instantiated two instances of reference clock and system PLL clock IP. The F-Tile Reference and System PLL Clocks Intel® FPGA IP parameter editor settings align with the System PLL frequency and PMA reference frequency parameter settings in the F-Tile Ethernet Intel FPGA Hard IP. If you generate the design example using Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own design example, you must manually instantiate this IP and connect all I/O ports.

    For information about supported system PLL modes, refer to F-Tile Ethernet Intel FPGA Hard IP User Guide. For information about this IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

  • Packet Client: Consists of a two instances of packet generator, a packet checker and a loopback client. The Packet Client generates various ROM-based traffic patterns for MAC mode and can loopback the RX and TX client side.
  • Avalon® memory-mapped interface Decoder: Decodes the Avalon® memory-mapped interface address to Hardware IP Top and PTP blocks if PTP is enabled. For base address for each of the Avalon® memory-mapped interface accessed instances, refer to Register Maps.