F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 4/01/2024
Document Table of Contents

1.2. Directory Structure

The F-Tile Ethernet Intel FPGA Hard IP core design example file directories contain the following generated files for the design example.
Figure 7. Directory Structure for F-Tile Ethernet Intel FPGA Hard IP Design ExampleThe <ethernet_mode> refers to the selected Ethernet mode in the IP tab of the IP parameter editor.
Table 4.  Directory and File Description
Directory/File Description
<design_example_dir>/hardware_test_design/eth_f_hw.qpf Quartus® Prime project file.
<design_example_dir>/hardware_test_design/eth_f_hw.qsf Quartus® Prime setting file.
<design_example_dir>/hardware_test_design/eth_f_hw.v Design example top-level HDL.
<design_example_dir>/hardware_test_design/eth_f_hw.sdc Synopsys Design Constraints (SDC) file.
<design_example_dir>/hardware_test_design/common Hardware design example support files.
<design_example_dir>/hardware_test_design/hwtest/main.tcl Main file for accessing System Console.
The Quartus® Prime software generates the design example files in the following folders:
  • <design_example_dir>/ex_<ethernet_rate>G: IP core files
  • <design_example_dir>/example_testbench: simulation files for testbench
  • <design_example_dir>/hardware_test_design: hardware test design files