F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 4/01/2024
Document Table of Contents

1.3.1. Fast Sim Model for FGT Variants

To provide a reduction in a real-time simulation duration, you can utilize a Fast Sim model in your design example testbench. For FGT variants, the model is enabled by a macro in the simulation run script.
To enable the Fast Sim model, add the following macro to your simulation run script:
The design example simulation script enables the macro by default for all FGT variants with the exception of variant auto-negotiation and link training.
  • In PTP variants, an additional switch must be defined a shown below.
    This switch enables the corrections for timestamp accuracy issues in the FGT fast sim model.
    Note: The FGT Fast Sim Model with PTP enabled can support up to 10,000 μs simulation time. If you run the simulation beyond this point, the simulation behaves unpredictably. This limitation is only for sim model.
  • The macro is not available for designs with enabled auto-negotiation and link training
  • You can achieve faster simulation times with auto-negotiation and link training enabled designs by running i_reconfig_clk at 10GHz. Furthermore, you can skip auto-negotiation and link training functionality and go directly to Data/Ethernet mode by writing to auto-negotiation and link training Control Status Registers (CSRs) or GUI parameters.
  • The macro appears in the example design simulation scripts for all the simulators only when you select FGT, and it is only applicable for FGT variants.

You can also add the macro to your simulation script for your own testbench.

Attention: In 53G PAM4 Ethernet IPs, you must set the serial clock input to the IP to the exact value of 37.648 ps for simulation to work correctly. This limitation does not apply to the design example simulations since the serial lines are in a loopback.