HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Document Table of Contents

5.6. Valid Video Data

You can generate video data using a different clock, other than vid_clk used in the HDMI TX core.

To generate video data, you need to use the actual pixel clock but vid_clk runs at a faster frequency. You can use a FIFO buffer to clock the data between the actual pixel clock and vid_clk while generating the valid video data (vid_valid) based on the inverted empty FIFO buffer.

For example, when operating at 8 Gbps link rate while transmitting 7680 x 4320p30 RGB resolution, a test pattern generator configured at 8 pixels in parallel runs at 148.5 MHz with the vid_clk domain of the HDMI TX core operating at 166.67 MHz. Like this case, not every vid_clk has valid video data. You can handle similar cases using the inverted empty signal of the DCFIFO.

When vid_clk runs at a faster frequency than the actual pixel clock frequency/pixels per clock, toggle vid_valid to qualify the video data.

Figure 37. Video Clock Running at Faster Frequency

When you connect the test pattern generator to the HDMI TX core which runs at a faster clock rate, you need to generate the vid_valid to qualify validity of the pixel data. There is a requirement for the vid_valid generation to ensure the video data evenly distributed across the link bandwidth. An example for the vid_valid generation is as below:

First, you need to calculate the ratio of the pixel rate to the vid_clk frequency. For example, 8Kp30 video at 8 pixels per clock which runs at vid_clk of 225Mhz, the ratio is

Then, you will need to create a logic to generate the vid_valid according to the calculated ratio. For the example above, the vid_valid should be evenly asserted for 33 clock cycles for every 50 clock cycles.

Figure 38. Timing diagram for the vid_valid generation

When vid_clk runs at the actual pixel clock frequency/pixels per clock, vid_valid should always remain asserted.

Figure 39. Video Clock Running at Actual Frequency