HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Document Table of Contents

5.1. Source Functional Description

The HDMI source core provides direct connection to the Transceiver Native PHY through a 20-bit or 40-bit parallel data path. The clock domains for the auxiliary and audio ports, and the internal modules are different for Support FRL = 1 and Support FRL = 0.
Figure 13. HDMI Source Signal Flow Diagram for TMDS (Support FRL = 0) DesignThe figure below shows the flow of the HDMI source signals. The figure shows the various clocking domains used within the core.

The source core provides four 20-bit parallel data paths corresponding to the 3 color channels and the clock channel.

The source core accepts video, audio, and auxiliary channel data streams. The core produces a scrambled and TMDS/TERC4 encoded data stream that would typically connect to the high-speed transceiver parallel data inputs.
Note: The scrambled data only applies for HDMI 2.0b stream with TMDS Bit Rate higher than 3.4 Gbps.

Central to the core is the Scrambler, TMDS/TERC4 Encoder. The encoder processes either video or auxiliary data.

Figure 14. HDMI Source Signal Flow Diagram for Support FRL = 1 Design and Active Video Protocol = None

For FRL path design, the video resampler and WOP generator operating at video clock domain accept video data running in the video clock (vid_clk) domain. The auxiliary data port, audio data port, and the auxiliary sideband signals also run in the video clock domain.

  • A DCFIFO clocks the HDMI data stream from the WOP generator in the video clock domain to the scrambler, TMDS/TERC4 encoder in the transceiver recovered clock (tx_clk) domain to create a TMDS data stream.
  • The HDMI data stream is also fed into the FRL path in FRL clock (frl_clk) domain to create an FRL data stream.

The multiplexer selects either TMDS data stream or FRL data stream as output data for lanes 0–3 based on the FRL rate.

  • If FRL rate is 0, the multiplexer selects TMDS data streams as output.
  • If FRL rate is non-zero, the multiplexer selects FRL data streams as output.
Figure 15. HDMI Source Signal Flow Diagram for Support FRL =1 and Active Video Protocol = AXIS-VVP Full