4.3.1.2. PLL Intel FPGA IP Cores

HDMI Intel® FPGA IP User Guide

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ID 683798

Date 3/07/2025

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Public

4.3.1.2. PLL Intel FPGA IP Cores

Use the PLL Intel FPGA IP core as the HDMI PLL to generate reference clock for RX or TX transceiver, link speed, and video clocks for the HDMI RX or TX IP core.

The HDMI PLL is referenced by the arbitrary TMDS clock. For HDMI source, you can reference the HDMI PLL by a separate clock source in the VIP passthrough design, which contains frame buffer. The HDMI PLL for TX has the same desired output frequencies as RX across symbols per clock and color depth.

For TMDS bit rates ranging from 3,400 Mbps to 6,000 Mbps (HDMI 2.0), the TMDS clock rate is 1/40 of the TMDS bit rate. The HDMI PLL generates reference clock for RX/TX transceiver at 4 times the TMDS clock.
For TMDS bit rates below 3,400 Mbps (HDMI 1.4b), the TMDS clock rate is 1/10 of the TMDS bit rate. The HDMI PLL generates reference clock for RX/TX transceiver at identical rate as the TMDS clock.

If the TMDS link operates at TMDS bit rates below the minimum RX/TX transceiver link rate, your design requires oversampling and a factor of 5 is chosen. The minimum link rate of the RX/TX transceiver vary across device families and symbols per clock. The HDMI PLL generates reference clock for RX/TX transceiver at 5 times the TMDS clock.

Note: Place the PLL Intel FPGA block on the transmit path (pll_hdmi_tx) in the physical location next to the transceiver PLL.

Table 15. HDMI PLL Desired Output Frequencies for 8-bpc VideoThis table shows an example of HDMI PLL desired output frequencies across various TMDS clock rates and symbols per clock for all supported device families using 8-bpc video.
Device Family	Symbols Per Clock	Minimum Link Rate (Mbps)	TMDS Bit Rate (Mbps)	Oversampling (5x) Required	TMDS Clock Rate (MHz)	RX/TX Transceiver Refclk (MHz)	RX/TX Link Speed Clock (MHz)	RX/TX Video Clock (MHz)
Arria V	2	611	270	Yes	27	135	13.5	13.5
			742.5	No	74.25	74.25	37.125	37.125
			1,485	No	148.5	148.5	74.25	74.25
			2,970	No	297	297	148.5	148.5
	4	1,000	270	Yes	27	135	6.75	6.75
			742.5	Yes	74.25	371.25	18.5625	18.5625
			1,485	No	148.5	148.5	37.125	37.125
			5,940	No	148.5	594	148.5	148.5
Stratix V	2	611	540	Yes	54	270	27	27
			1,620	No	162	162	81	81
			5,934	No	148.35	593.4	296.7	296.7

The color depths greater than 8 bpc or 24 bpp are defined to be deep color. For a color depth of 8 bpc, the core carries the pixels at a rate of one pixel per TMDS clock. At deeper color depths, the TMDS clock runs faster than the source pixel clock to provide the extra bandwidth for the additional bits.

The TMDS clock rate is increased by the ratio of the pixel size to 8 bits:

8 bits mode—TMDS clock = 1.0 × pixel or video clock (1:1)
10 bits mode—TMDS clock = 1.25 × pixel or video clock (5:4)
12 bits mode—TMDS clock = 1.5 × pixel or video clock (3:2)
16 bits mode—TMDS clock = 2 × pixel or video clock (2:1)

Table 16. HDMI PLL Desired Output Frequencies for Deep Color VideoThis table shows an example of HDMI PLL desired output frequencies across symbols per clock and color depths.
Symbols Per Clock	Oversampling (5x) Required	Bits Per Component	TMDS Bit Rate (Mbps) ³	TMDS Clock Rate (MHz)	RX/TX Transceiver Refclk (MHz)	RX/TX Link Speed Clock (MHz)	RX/TX Video Clock (MHz)
2	Yes	8	270	27	135	13.5	13.5
		10 ⁴	337.5	33.75	168.75	16.875	13.5
		12 ⁴	405	40.5	202.5	20.25	13.5
		16 ⁴	540	54	270	27	13.5
4	No	8	1,485	148.5	148.5	37.125	37.125
		10 ⁴	1,856.25	185.625	185.625	46.40625	37.125
		12 ⁴	2,227.5	222.75	222.75	55.6875	37.125
		16 ⁴	2,970	297	297	74.25	37.125

The default frequency setting of the HDMI PLL is fixed at possible maximum value for each clock for appropriate timing analysis.

Note: This default combination is not valid for any HDMI resolution. The core will reconfigure to the appropriate settings upon power up.

³ The TMDS bit rate is 10x the TMDS character rate. For information about how the TMDS character rate is derived from the pixel clock rate, refer to the HDMI Specifications.

⁴ For this release, deep color video is only demonstrated in VIP bypass mode. It is not available in VIP passthrough mode.

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4.3.1.2. PLL Intel FPGA IP Cores