HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Document Table of Contents

5.1.26. TX AXI4-Stream Auxiliary Arbiter

The packet arbiter allows multiple data packet sources to access the HDMI transmitter auxiliary packet interface port. Equal priority is given to each source, with each port selected on a round-robin basis.

Functionally, the arbiter samples the level of each axi4s_aux_in_tvalid input in turn on every clock cycle. axi4s_aux_in_tvalid high indicates the channel has a data packet available. The arbiter selects this input pass data through to the output until axi4s_aux_in_tlast goes high, indicating the end of the packet. It then return to sampling each channel.

This arbiter arbitrates between auxiliary data from TX auxiliary user packet configured from the HDMI register by the host processor and the TX AXI auxiliary bridge.