HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Document Table of Contents IRQ_STATUS (0x01)

Table 67.  IRQ_STATUS (0x01)
Name Bit(s) Access Description Reset
Reserved 31:4
Video overflow 3 W1C Indicates if the FIFO clocking the data from the video path to the FRL path is overflowing.

Applicable only for FRL mode.

Hotplug detect 2 W1C Indicates the status of the hotplug detect (HPD) input 0x0
Reserved 1:0