HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Document Table of Contents IRQ_MASK (0x02)

Table 68.  IRQ_MASK (0x02)
Name Bit(s) Access Description Reset
Reserved 31:4
Video overflow mask 3 RW Mask the video overflow input interrupt 0x0
Hotplugdetect mask 2 RW Mask the hotplug detect (HPD) input interrupt 0x0
Reserved 1:0