HDMI Intel® FPGA IP User Guide

ID 683798
Date 11/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.1.1. Transceiver Native PHY (RX)

  • Transceiver Native PHY in Arria V devices
    • To operate the TMDS bit rate up to 3,400 Mbps, configure the Transceiver Native PHY at 20 bits at PCS – PLD interface with the HDMI RX core at 2 symbols per clock. When the PCS – PLD interface width is 20 bits, the minimum link rate is 611 Mbps.
    • To operate the TMDS bit rate up to 6,000 Mbps, configure the Transceiver Native PHY at 40 bits with the HDMI RX core at 4 symbols per clock. When the PCS – PLD interface width is 40 bits, the minimum link rate is 1,000 Mbps.
    • Oversampling is required for TMDS bit rate which is below the minimum link rate.
  • Transceiver Native PHY in Stratix V devices
    • To operate the TMDS bit rate up to 6,000 Mbps, configure the Transceiver Native PHY at 20 bits at PCS – PLD interface with the HDMI RX core at 2 symbols per clock. When the PCS – PLD interface width is 20 bits, the minimum link rate is 611 Mbps.
Table 11.  Arria V and Stratix V Transceiver Native PHY (RX) Configuration Settings (6,000 Mbps)This table shows an example of Arria V and Stratix V Transceiver Native PHY (RX) configuration settings for TMDS bit rate of 6,000 Mbps.
Parameters Settings
Datapath Options
Enable TX datapath Off
Enable RX datapath On
Enable Standard PCS On
Initial PCS datapath selection Standard
Number of data channels 3
Enable simplified data interface On
RX PMA
Data rate 6,000 Mbps
Enable CDR dynamic reconfiguration On
Number of CDR reference clocks 2 4
Selected CDR reference clock 0 4
Selected CDR reference clock frequency 600 MHz
PPM detector threshold 1,000 PPM
Enable rx_pma_clkout port On
Enable rx_is_lockedtodata port On
Enable rx_is_lockedtoref port On
Enable rx_set_locktodata and rx_set_locktoref ports On
Standard PCS
Standard PCS protocol Basic
Standard PCS/PMA interface width
  • 10 (for 1 symbol per clock)
  • 20 (for 2 and 4 symbols per clock)
Enable RX byte deserializer
  • Off (for 1 and 2 symbols per clock)
  • On (for 4 symbols per clock)
Table 12.  Arria V and Stratix V Transceiver Native PHY (RX) Common Interface PortsThis table describes the Arria V and Stratix V Transceiver Native PHY (RX) common interface ports.
Signals Direction Description
Clocks
rx_cdr_refclk[1:0] Input

Input reference clock for the RX CDR circuitry.

  • To support arbitrary wide data rate range from 250 Mbps to 6,000 Mbps, you need a generic core PLL to obtain a higher clock frequency from the TMDS clock. You need a higher clock frequency to create oversampled stream for data rates below the minimum transceiver data rate—for example, 611 Mbps or 1,000 Mbps).
  • If the TMDS clock pin is routed to the transceiver dedicated reference clock pin, you only need to create one transceiver reference clock input. You can use the TMDS clock as reference clock for a generic core PLL to drive the transceiver.
  • If you use Bitec HDMI HSMC 2.0 daughter card, the TMDS clock pin is routed to the transceiver serial data pin. In this case, to use the TMDS clock as a reference clock for a generic core PLL, the clock must also drive the transceiver dedicated reference clock. Connect bit 0 to the generic core PLL output and bit 1 to the TMDS clock and set the selected CDR reference clock at 0.
rx_std_clkout[2:0] Output

RX parallel clock output.

  • The CDR circuitry recovers the RX parallel clock from the RX data stream when the CDR is configured at lock-to-data mode.
  • The RX parallel clock is a mirror of the CDR reference clock when the CDR is configured at lock-to-reference mode.
rx_std_coreclkin[2:0] Input

RX parallel clock that drives the read side of the RX phase compensation FIFO.

Connect to rx_std_clkout ports.

rx_pma_clkout[2:0] Output

RX parallel clock (recovered clock) output from PMA.

Leave unconnected.

Resets
rx_analogreset[2:0] Input

Active-high, edge-sensitive, asynchronous reset signal.

When asserted, resets the RX CDR circuit, deserializer.

Connect to Transceiver PHY Reset Controller IP core.

rx_digitalreset[2:0] Input

Active-high, edge-sensitive, asynchronous reset signal.

When asserted, resets the digital component of the RX data path.

Connect to the Transceiver PHY Reset Controller IP core.

PMA Ports
rx_set_locktoref[2:0] Input

When asserted, programs the RX CDR to lock to reference mode manually. The lock to reference mode enables you to control the reset sequence using rx_set_locktoref and rx_set_locktodata.

The Multirate Reconfiguration Controller (RX) sets this port to 1 if oversampling mode is required. Otherwise, this port is set to 0.

Refer "Transceiver Reset Sequence" in Transceiver Reset Control in Arria V/Stratix V Devices for more information about manual control of the reset sequence.
rx_set_locktodata[2:0] Input Always driven to 0. When rx_set_locktoref is driven to 1, the CDR is configured to lock-to-reference mode. Otherwise, the CDR is configured to lock-to-data mode.
rx_is_lockedtoref[2:0] Output When asserted, the CDR is locked to the incoming reference clock. Connect this port to rx_is_lockedtodata port of the Transceiver PHY Reset Controller IP core when rx_set_locktoref is 1.
rx_is_lockedtodata[2:0] Output When asserted, the CDR is locked to the incoming data. Connect this port to rx_is_lockedtodata port of Transceiver PHY Reset Controller IP core when rx_set_locktoref is 0.
rx_serial_data[2:0] Input RX differential serial input data.
PCS Ports
unused_rx_parallel_data Output Leave unconnected.
rx_parallel_data[S*3*10-1:0] Output PCS RX parallel data.
Note: S=Symbols per clock.
Calibration Status Port
rx_cal_busy[2:0] Output When asserted, indicates that the initial RX calibration is in progress. This port is also asserted if the reconfiguration controller is reset. Connect to the Transceiver PHY Reset Controller IP core.
Reconfiguration Ports
reconfig_to_xcvr[209:0] Input Reconfiguration signals from the Transceiver Reconfiguration Controller.
reconfig_from_xcvr[137:0] Output Reconfiguration signals to the Transceiver Reconfiguration Controller.
4 The Bitec HDMI HSMC 2.0 daughter card routes the TMDS clock pin to the transceiver serial data pin. To use the TMDS clock to drive the HDMI PLL, the TMDS clock must also drive the transceiver dedicated reference clock pin. The number of CDR reference clocks is 2 with reference clock 1 (unused) driven by the TMDS clock and reference clock 0 driven by the HDMI PLL output clock. The selected CDR reference clock will be fixed at 0.

Did you find the information on this page useful?

Characters remaining:

Feedback Message