HDMI Intel® FPGA IP User Guide

ID 683798
Date 11/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.11. FRL Depacketizer

FRL depacketizer reconstructs the FRL packets into HDMI data.

FRL depacketizer contains a mixed-width DCFIFO to clock the data from the frl_clk domain to the vid_clk domain. This block also demaps the HDMI data from number of FRL characters per clock * 16 bits to pixels per clock * 24 bits, where number of FRL characters per clock is always 16 and pixels per clock is always 8 in FRL mode.