HDMI Intel® FPGA IP User Guide

ID 683798
Date 11/12/2021
Public

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4.3.1.14.2. Source SCDC Controller

The source SCDC Controller contains the I2C master controller. The I2C master controller transfers the SCDC data structure from the FPGA source to the external sink for HDMI 2.0b operation.

For example, if the outgoing data stream is 6,000 Mbps, the Nios II processor commands the I2C master controller to update the TMDS_Bit_Clock_Ratio and Scrambler_Enable bits of the sink TMDS configuration register to 1. The same I2C master can also transfer the DDC data structure (E-EDID) between the HDMI source and external sink.

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