HDMI Intel® FPGA IP User Guide

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ID 683798
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

5.1.8.2. Audio Metadata Bundle Bit-Fields

The Audio Metadata (AM) packet carries additional information related to 3D Audio and Multi-Stream Audio (MST).

The core sends the AM packet on the active edge of the V-SYNC signal to ensure that the packet is sent once per field. The signal bundle of audio_metadata[165:0] is clocked by ls_clk for Support FRL = 0 designs and by vid_clk for Support FRL = 1 designs.

Table 28.  Audio Metadata Bundle Bit-Fields for Packet Header and Control

Table below lists the AM signal bit-fields for packet header (as described in the HDMI 2.0b Specification Section 8.3) and control.

Bit-field Name Description
0 3D_AUDIO
  • 1: Transmits 3D audio
  • 0: Transmits MST audio
2:1 NUM_VIEWS Number of views for an MST stream
4:3 NUM_AUDIO_STR Number of audio streams - 1
165 Control Disables the core from inserting the AM packet.
  • 1: The core does not insert audio_metadata[164:0]. The AM packet on the Auxiliary Data Port passes through.
  • 0: The core inserts audio_metadata[164:0] when audio format[3:0] is 3D audio or MST audio. The core filters the AM packet on the Auxiliary Data Port.
Table 29.  Audio Metadata Bundle Bit-Fields for Packet Content when 3D_AUDIO = 1

Table below lists the AM signal bit-fields for packet content when 3D_AUDIO = 1 (as described in the HDMI 2.0b Specification Section 8.3.1).

Bit-field Name Description
9:5 3D_CC Channel count of the transmitted 3D audio
12:10 Reserved Reserved (0)
16:13 ACAT Audio channel allocation standard
20:17 Reserved Reserved (0)
28:21 3D_ACAT Channel/Speaker allocation for 3D audio
164:29 Reserved Reserved (0)
Table 30.  Audio Metadata Bundle Bit-Fields for Packet Content when 3D_AUDIO = 0

Table below lists the AM signal bit-fields for packet content when 3D_AUDIO = 0 (as described in the HDMI 2.0b Specification Section 8.3.2).

Bit-field Name Description
5 Multiview_Left_0 Left stereoscopic picture (Subpacket 0 in MST Audio Sample Packet)
6 Multiview_Right_0 Right stereoscopic picture (Subpacket 0 in MST Audio Sample Packet)
12:7 Reserved Reserved (0)
15:13 Suppl_A_Type_0 Supplementary audio type (Subpacket 0 in MST Audio Sample Packet)
16 Suppl_A_Mixed_0 Mix of main audio components and a supplementary audio track (Subpacket 0 in MST Audio Sample Packet)
17 Suppl_A_Valid_0 Audio stream contains a supplementary audio track (Subpacket 0 in MST Audio Sample Packet)
19:18 Reserved Reserved (0)
20 LC_Valid_0 Validity of Language_Code (Subpacket 0 in MST Audio Sample Packet)
44:21 Language_Code_0 Audio stream language (Subpacket 0 in MST Audio Sample Packet)
45 Multiview_Left_1 Left stereoscopic picture (Subpacket 1 in MST Audio Sample Packet)
46 Multiview_Right_1 Right stereoscopic picture (Subpacket 1 in MST Audio Sample Packet)
52:47 Reserved Reserved (0)
55:53 Suppl_A_Type_1 Supplementary audio type (Subpacket 1 in MST Audio Sample Packet)
56 Suppl_A_Mixed_1 Mix of main audio components and a supplementary audio track (Subpacket 1 in MST Audio Sample Packet)
57 Suppl_A_Valid_1 Audio stream contains a supplementary audio track (Subpacket 1 in MST Audio Sample Packet)
59:58 Reserved Reserved (0)
60 LC_Valid_1 Validity of Language_Code (Subpacket 1 in MST Audio Sample Packet)
84:61 Language_Code_1 Audio stream language (Subpacket 1 in MST Audio Sample Packet)
85 Multiview_Left_2 Left stereoscopic picture (Subpacket 2 in MST Audio Sample Packet)
86 Multiview_Right_2 Right stereoscopic picture (Subpacket 2 in MST Audio Sample Packet)
92:87 Reserved Reserved (0)
95:93 Suppl_A_Type_2 Supplementary audio type (Subpacket 2 in MST Audio Sample Packet)
96 Suppl_A_Mixed_2 Mix of main audio components and a supplementary audio track (Subpacket 2 in MST Audio Sample Packet)
97 Suppl_A_Valid_2 Audio stream contains a supplementary audio track (Subpacket 2 in MST Audio Sample Packet)
99:98 Reserved Reserved (0)
100 LC_Valid_2 Validity of Language_Code (Subpacket 2 in MST Audio Sample Packet)
124:101 Language_Code_2 Audio stream language (Subpacket 2 in MST Audio Sample Packet)
125 Multiview_Left_3 Left stereoscopic picture (Subpacket 3 in MST Audio Sample Packet)
126 Multiview_Right_3 Right stereoscopic picture (Subpacket 3 in MST Audio Sample Packet)
132:127 Reserved Reserved (0)
135:133 Suppl_A_Type_3 Supplementary audio type (Subpacket 3 in MST Audio Sample Packet)
136 Suppl_A_Mixed_3 Mix of main audio components and a supplementary audio track (Subpacket 3 in MST Audio Sample Packet)
137 Suppl_A_Valid_3 Audio stream contains a supplementary audio track (Subpacket 3 in MST Audio Sample Packet)
139:138 Reserved Reserved (0)
140 LC_Valid_3 Validity of Language_Code (Subpacket 3 in MST Audio Sample Packet)
164:141 Language_Code_3 Audio stream language (Subpacket 3 in MST Audio Sample Packet)
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