HDMI Intel® FPGA IP User Guide

ID 683798
Date 11/12/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.4. Link Training Procedure

The HDMI TX core does not handle the link training process.

Instead, the Nios® II software manages the link training process, which is demonstrated in the Intel® Arria® 10/ Intel® Stratix® 10 FRL design example.

Implement the link training external to the HDMI TX core according to the TX link training flow diagram shown below. The HDMI TX core generates different link training patterns on each lane based on your input through the scdc_frl_pattern port when scdc_frl_start is deasserted. When scdc_frl_start is asserted, the source core generates normal video.

Figure 33. Source Link Training Flow Diagram

Did you find the information on this page useful?

Characters remaining:

Feedback Message