HDMI Intel® FPGA IP User Guide

ID 683798
Date 11/12/2021
Public

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5.1.9. HDCP 1.4 TX Architecture

The HDCP 1.4 transmitter block encrypts video and auxiliary data prior to the transmission over serial link that has HDCP 1.4 device connected.
The HDCP 1.4 TX core consists of the following entities:
  • Control and Status Registers Layer
  • Authentication Layer
  • Video Stream and Auxiliary Layer
Figure 26. Architecture Block Diagram of HDCP 1.4 TX IP

The Nios II processor typically drives the HDCP 1.4 TX core. The processor implements the authentication protocol. The processor accesses the IP through the Control and Status Port using Avalon Memory Mapped (Avalon-MM) interface.

The HDCP specifications requires the HDCP 1.4 TX core to be programmed with the DCP-issued production keys – Device Private Keys (Akeys) and Key Selection Vector (Aksv). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port. The on-chip memory must store the key data in the arrangement in the table below.

Table 31.  HDCP 1.4 TX Key Port Addressing
Address Content
6'h28 {16’d0, Aksv[39:0]}
6'h27 Akeys39[55:0]
6'h26 Akeys38[55:0]
... ...
6'h01 Akeys01[55:0]
6'h00 Akeys00[55:0]

When authenticating with the HDCP 1.4 repeater device, the HDCP 1.4 TX core must perform the second part of the authentication protocol. This second part corresponds to the computation of the SHA-1 hash digest for all downstream device KSVs which are written to the registers in Control and Status Register Layer using the Control and Status Port (Avalon-MM).

The Video Stream and Auxiliary layer receives audio and video content over its Video and Aux Data Input Port, and performs the encryption operation. The Video Stream and Auxiliary Layer detects the Encryption Status Signaling (ESS) provided by the HDMI TX core to determine when to encrypt frames.

You can use the HDCP 1.4 registers to customize your design configurations. The HDCP 1.4 TX core supports full handshaking mechanism for authentication. Every issued command should be followed by polling of the assertion of its corresponding status bit before proceeding to issuing the next command. The value of AUTH_CMD must be in one-hot format that only one bit can be set at a time.

Table 32.  HDCP 1.4 TX Registers Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 AUTH_CMD (one-hot) WO 0x00000000 31:6 Reserved Reserved.
5 GO_V Set to 1 to compute V and compare against V’ during authentication with repeater. Self-cleared.
4 Reserved Reserved.
3 GEN_RI Set to 1 to generate and receive R0 during authentication exchange or Ri during link integrity verification. Ri-Ri’ comparison should be performed by Nios® II processor. Self-cleared.
2 GO_KM Set to 1 to compute master key (km). Self-cleared.
1 GEN_AKSV Set to 1 to request and receive Aksv. Self-cleared.
0 GEN_AN Set to 1 to generate and receive new true random An. Self-cleared.
0x01 AUTH_MSGDATAIN WO 0x00000000 31:8 Reserved Reserved.
7:0 MSGDATAIN

Write messages (in byte) from receiver in burst mode.

  1. Master key computation: Prior to setting GO_KM to 1, the BCAPS.REPEATER bit had to be set and the following messages had to be written in this sequence:
    1. 5 bytes of Bksv with least significant byte (lsb) first.
  2. V generation: Prior to setting GO_V to 1, the following messages had to be written in this sequence:
    1. 20 bytes of V’ with lsb first
    2. Variable length of KSV list with lsb first
    3. 2 bytes of Bstatus with lsb first
0x02 AUTH_STATUS RO 0x00000000 31 KM_OK Asserted by the core to indicate the received Bksv is valid. Poll KM_DONE until it is set before reading KM_OK.
30 V_OK Asserted by the core to indicate V-V’ comparison is passed. Poll V_DONE until it is set before reading V_OK.
29:6 Reserved Reserved.
5 V_DONE Asserted by the core when V is generated. Self-cleared upon next GO_V is set.
4 Reserved Reserved
3 RI_DONE Asserted by the core when Ri is generated. Self-cleared upon next GEN_RI is set.
2 KM_DONE Asserted by the core when Km is generated. Self-cleared upon next GO_KM is set.
1 AKSV_DONE Asserted by the core when Aksv is ready to be read from MSGDATAOUT. Self-cleared upon next GEN_AKSV is set.
0 AN_DONE Asserted by the core when new random An is generated and ready to be read from MSGDATAOUT. Self-cleared upon next GEN_AN is set.
0x03 AUTH_MSGDATAOUT RO 0x00000000 31:8 Reserved Reserved.
7:0 MSGDATAOUT

Read messages (in byte) from the IP in burst mode.

  1. An generation: When AN_DONE is set to 1, reading this offset 8 times to obtain An with lsb first.
  2. Aksv request: When AKSV_DONE is set to 1, reading this offset 5 times to obtain Aksv with lsb first.
  3. Ri request: When RI_DONE is set to 1, reading this offset 2 times to obtain Ri with lsb first.
0x04 VID_CTL RW 0x00000000 31:1 Reserved Reserved.
0 HDCP_ENABLE Set to 1 to enable HDCP 1.4 encryption. Set to 0 if HDCP 1.4 encryption is not required especially when it is in unauthenticated state.
0x05 BCAPS RW 0x00000000 31:2 Reserved Reserved.
1 REPEATER Downstream repeater capability. Write bit 6 (REPEATER) of Bcaps received from downstream to this offset.
0 Reserved Reserved.

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