5.1. Source Functional Description
The source core provides four 20-bit parallel data paths corresponding to the 3 color channels and the clock channel.
Central to the core is the Scrambler, TMDS/TERC4 Encoder. The encoder processes either video or auxiliary data.
For FRL path design, the video resampler and WOP generator operating at video clock domain accept video data running in the video clock (vid_clk) domain. The auxiliary data port, audio data port, and the auxiliary sideband signals also run in the video clock domain.
- A DCFIFO clocks the HDMI data stream from the WOP generator in the video clock domain to the scrambler, TMDS/TERC4 encoder in the transceiver recovered clock (tx_clk) domain to create a TMDS data stream.
- The HDMI data stream is also fed into the FRL path in FRL clock (frl_clk) domain to create an FRL data stream.
The multiplexer selects either TMDS data stream or FRL data stream as output data for lanes 0–3 based on the FRL rate.
- If FRL rate is 0, the multiplexer selects TMDS data streams as output.
- If FRL rate is non-zero, the multiplexer selects FRL data streams as output.
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