AN 872: Thermal and Power Guidelines: For Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683795
Date 8/30/2019
Public

3.3. Measuring the Real Static Power

Leakage current is a leading cause of board-to-board power consumption variation. The power measurements from the above section include power due to leakage current (static power) and power due to the AFU logic (dynamic power). In this section, you will measure the static power of the board-under-test in order to understand the dynamic power.

Before measuring the FPGA static power, use the disable-gpio-input-buffer-intel-pac-arria10-gx.tcl script (download) to process the FPGA programming file, (*.sof file) which contains a FIM and AFU design. The tcl script disables all FPGA input pins to ensure that there is no toggling inside the FPGA (which means no dynamic power). Refer to the Minimal Flow Example to compile a sample AFU. The generated *.sof file is located at:
cd $OPAE_PLATFORM_ROOT/hw/samples/<afu name>
$ OPAE_PLATFORM_ROOT/hw/samples/<afu name>build_synth/build/output_files/afu_*.sof

You must save the disable-gpio-input-buffer-intel-pac-arria10-gx.tcl in the above directory and then run the following command:

# quartus_asm -t disable-gpio-input-buffer-intel-pac-arria10-gx.tcl afu_*.sof
Sample output:
Info: ******************************************************************* Info: Running Quartus Prime Assembler
Info: Version 17.1.1 Build 273 12/19/2017 SJ Pro Edition
Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details.
Info: Processing started: Thu Aug 23 13:10:48 2018 Info: Command: quartus_asm -t disable-gpio-input-buffer-intel-pac-arria10-gx.tcl Assembler: Post processing afu_fit.sof
Assembler : Post processing gpio_0_0 Assembler : Post processing gpio_0_1 Assembler : Post processing gpio_0_2 Assembler : Post processing gpio_0_3 Assembler : Post processing gpio_0_4 Assembler : Post processing gpio_0_5 Assembler : Post processing gpio_0_6 Assembler : Post processing gpio_0_7 Assembler : Post processing gpio_1_0 Assembler : Post processing gpio_1_1 Assembler : Post processing gpio_1_2 Assembler : Post processing gpio_1_3 Assembler : Post processing gpio_1_4 Assembler : Post processing gpio_1_5 Assembler : Post processing gpio_1_6 Assembler : Post processing gpio_1_7
Info (23030): Evaluation of Tcl script disable-gpio-input-buffer-intel-pac-arria10-gx.tcl was
successful
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1128 megabytes
Info: Processing ended: Thu Aug 23 13:10:59 2018 Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:05

Upon successful execution of the tcl script, the afu_*.sof file is updated and ready for FPGA programming.

Follow these steps to measure the real static power:
  1. Use the Intel® Quartus® Prime programmer to program the *.sof file. Refer to the Using the Intel Quartus Prime Programmer for detailed steps.
  2. Monitor the FPGA core temperature, voltage, and current using the BWMonitor tool. Enter these values in row Step 2: FPGA core static power measurement of the Intel® FPGA PAC Power Estimator Sheet.

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