SmartVID Controller IP Core User Guide

ID 683770
Date 5/08/2017

3. SmartVID Functional Description

The SmartVID Controller IP core connects to the other sub-systems in a device.
Figure 1. SmartVID Controller Block DiagramThe figure below shows a block diagram of the SmartVID Controller IP core.

Table 2.  SmartVID Controller Interfaces
Interface Description
Clock Reset
  • The SmartVID controller requires vid_clk at 125 MHz and jtag_core_clk at 25 MHz.
  • Deassert vid_rst_b and vid_jtag_rst_b after vid_clk and jtag_core_clk have each toggled for at least 10 clock cycles.
    Note: The vid_jtag_rst_b vid_rst_b signals are independent of their respective clocks.
JTAG Uses the JTAG interface to retrieve the fuse value from the JTAG atom on an Arria 10 device.
Temperature Sensor Uses the temperature sensor to sample the temperature code for the SmartVID controller operation.
Avalon Control and Status Register (CSR) To change the control and status register values on the fly (for advance users).
Parallel/User Logic To interface with the user logic.

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