SmartVID Controller IP Core User Guide

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ID 683770
Date 5/08/2017
Public

5. SmartVID Controller Control and Status Registers

The SmartVID Controller control and status registers are meant for advanced users.

The SmartVID Controller IP core uses the Avalon Memory-Mapped (Avalon-MM) interface for read and write operations in a memory-mapped system. The 32-bit non-bursting Avalon-MM slave interface allows upstream to access internal control and status registers.

The SmartVID Controller IP supports a basic one clock cycle transaction bus. Avalon-MM slave interface does not support byte enable access. Avalon-MM slave read and write data width is 32 bits (DWORD access).

Note: The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.
Table 4.  SmartVID Controller Control and Status Register MapThe table below lists the control and status registers for the SmartVID Controller IP core.
Address Offset Register Description
0x0 Capabilities and Control 1 (CC1) Configures the capabilities of the SmartVID feature.
0x1 Capabilities and Control 2 (CC2)
0x2 Capabilities and Control 3 (CC3)
0x3 VID Fuse1 (VF1) Stores VID fuse values [31:0]
0x4 VID Fuse2 (VF2) Stores VID fuse values [63:32]
0x5 Temperature and Computed VID Codes (TCVC) Stores a sampled temperature code, and a computed VID code.
Table 5.  Capabilities and Control 1 (CC1) Register
Address Register RO/RW Description
31:2 Reserved RO This register is reserved for future use.
1 Temperature Sensor Enable RW A policy bit that governs whether the temperature sensor of the Arria 10 device is enabled in user mode.
  • 0: Temperature sensor is disabled.
  • 1: Temperature sensor is enabled (default).
Note: The temperature codes from the temperature sensor are also used by other Arria 10 sub-systems. Clear this bit only if enabling the temperature sensor may cause unexpected issues to the Arria 10 device.
0 SmartVID Controller Start Operations (VID_OP_START) RW A policy bit that determines whether the IP core can start operating when it is out of reset.
Note: Set this to 1 only after programming all other configuration registers for this IP core.
Table 6.  Capabilities and Control 2 (CC2) Register
Address Register RO/RW Description
31:27 Reserved RO This register is reserved for future use.
26:21 VID Step Size (VID_STEP) RW

These bits determine the final adjustment magnitude of the computed VID code at the end of each computation, if applicable. Each step represents a 5 mV change.

20:1 VID Computation Delay (VID_COMPUTE_DELAY) RW These bits represent the duration that must elapse (in µs) before a new VID code is computed. The legal range for the delay is 10 ms to 1048 ms.

Ensure that this computation delay is longer than the time required for the following tasks:

  • The time the user logic or controller takes to complete receiving the VID value, including the retry upon error.
  • The time the voltage regulator takes to reach the voltage represented by the VID value.
Note: For optimum system considerations, you are recommended to program this computation delay to 10 ms, 100 ms, or 1 second interval, instead of at µs range. For example, 10 ms (10,000 µs) = 00000010011100010000 (2710h).
0 Dynamic SmartVID Feature Control (DYN_AVS_CONTROL) RW This bit dynamically enables or disables the SmartVID feature.
  • 0: SmartVID feature is disabled.
  • 1: SmartVID feature is enabled (default).
Note: The SmartVID logic in the IP core is only enabled when CC2[0], CC3[3], CC3[16], and VF1[4] bits are 1.
Table 7.  Capabilities and Control 3 (CC3) Register
Address Register RO/RW Description
31:17 Reserved RO This register is reserved for future use.
16 Device Supports SmartVID Feature (DEVICE_SUPPORTS_AVS) RO This policy bit determines if the SmartVID feature can be enabled.
  • 0: SmartVID feature is not supported.
  • 1: SmartVID feature is supported.
15:10 Live VID Code (VID_DEFAULT) RO This bit indicates the live VID code produced by the SmartVID Controller IP core. This live code may be in either static mode or SmartVID mode.
9:4 Default VID Value (VID_DEFAULT) RO These bits indicate the default VID value.
3 SmartVID Feature Enable (AVS_ENABLE) RO This policy bit determines if the SmartVID feature can be enabled.
2:1 Core Speed Grade (CORE_SPEED_GRADE) RO
These bits indicate the core fabric speed grade of the FPGA device.
Bits Speed Grade
00 –3
11 –2
10 –1
01 Reserved
0 Reserved RO This register is reserved for future use.
Table 8.  VID Fuse1 (VF1) Register
Address Register RO/RW Description
31 Reserved RO This register is reserved for future use.
30 VID Fuses Valid RO This bit indicates whether the non-reserved fields of this register have valid values or not.
  • 0: Values of non-reserved fields of this register are invalid.
  • 1: Values of non-reserved fields of this register are valid.
29:24 VID for –1 Core Speed Grade RO These bits are mapped to the retrieved VID Fuse[29:24], which represent the VID code for –1 core speed grade.

Refer to VID Codes for Arria 10 Speed Grades.

23:22 Reserved RO This register is reserved for future use.
21:16 VID for –2 Core Speed Grade RO These bits are mapped to the retrieved VID Fuse[21:16], which represent the VID code for –2 core speed grade.

Refer to VID Codes for Arria 10 Speed Grades.

15:14 Reserved RO This register is reserved for future use.
13:8 VID for –3 Core Speed Grade RO These bits are mapped to the retrieved VID Fuse[13:8], which represent the VID code for –3 core speed grade.

Refer to VID Codes for Arria 10 Speed Grades.

7:5 Reserved RO This register is reserved for future use.
4 SmartVID Feature Enable Via Fuse RO This bit is mapped to the retrieved VID Fuse[4], which determines if the SmartVID feature of the IP core can be supported.
  • 0: SmartVID feature is not supported.
  • 1: SmartVID feature is supported.
3:0 Reserved RO This register is reserved for future use.
Table 9.  Temperature and Computed VID Codes (TCVC) Register
Address Register RO/RW Description
31:28 Reserved RO This register is reserved for future use.
27 SmartVID Status RO This bit indicates the operating state of the SmartVID feature in the .
  • 0: SmartVID logic is deactivated.
  • 1: SmartVID logic is active.
26:17 Temperature Used In SmartVID Computation RO These bits capture the temperature code used in the latest computed VID code when SmartVID logic is active. This information is intended for correlation and debugging purposes.
Note: These bits are set to 0 if CC1[1] and CC1[2] bits are 0 and the SmartVID logic is deactivated.
16 Temperature Code Valid RO This bit indicates whether TCVC[9:0] has a valid temperature code.
  • 0: TCVC[9:0] value is invalid.
  • 1: TCVC[9:0] value is valid.
Note: This bit is set to 0 if CC1[1] is 0.
15:10 Latest Computed VID Code in SmartVID mode RO These bits indicate the latest computed VID code when SmartVID logic is active. When SmartVID logic is deactivated, these bits will be set to 0.
9:0 Temperature Code RO These bits indicate the periodically sampled temperature code output by the temperature sensor.
Note: These bits are set to 0 if CC1[1] is 0.

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