SmartVID Controller IP Core User Guide

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ID 683770
Date 5/08/2017
Public

4. SmartVID Controller Interface Signals

The SmartVID Controller IP core uses the interface signals to connect with the other sub-systems in the Arria 10 device.
Table 3.  Input and Output Signals for the SmartVID Controller IP Core
Signal Direction Description
vid_clk Input Must be 125 MHz. Most of the functional blocks in the IP core use this clock.
jtag_core_clk Input Must be 25 MHz. The fuse-read logic in the IP core uses this clock.
vid_rst_b Input An active-low reset synchronized to vid_clk domain.
vid_jtag_rst_b Input An active-low reset synchronized to jtag_core_clk domain.
vidctl_avmm_address[2:0] Input The Avalon-MM Master address for data transfer to/from SmartVID controller. This is a word address.
vidctl_avmm_read Input Read-transfer indication from the Avalon-MM Master to the SmartVID controller.
vidctl_avmm_readdata[31:0] Output Read data from SmartVID controller to Avalon-MM Master.
vidctl_avmm_write Input Write-transfer indication from the Avalon-MM Master to the SmartVID controller.
vidctl_avmm_writedata[31:0] Input Write data from the Avalon-MM Master to the SmartVID controller.
vidctl_vid_ack Input Acknowledge pulse of the vidctl_vid_code signal.
vidctl_temp[9:0] Input Connect this signal to the tempout port of the temperature sensor. This is the temperature code output from temperature sensor.
vidctl_eoc Input Connect this signal to the eoc port of the temperature sensor. This is the end of conversion signal from temperature sensor.
vidctl_tdocore Input Connect this signal to the tdocore port of the JTAG atom.
vidctl_ntrstcore Output Connect this signal to the ntrstcore port of the JTAG atom.
vidctl_tckcore Output Connect this signal to the tckcore port of the JTAG atom.
vidctl_corectl_jtag Output Connect this signal to the corectl port of the JTAG atom. Dynamic FPGA core firewall enable.
vidctl_tmscore Output Connect this signal to the tmscore port of the JTAG atom.
vidctl_tdicore Output Connect this signal to the tdicore port of the JTAG atom.
vidctl_temp_sense_enable Output Connect this signal to the corectl port of the temperature sensor. This is a core enable signal from the core to the temperature sensor.
vidctl_temp_sense_reset Output Connect this signal to the reset port of the temperature sensor. This is the reset signal from the core to the temperature sensor.
vidctl_vid_code_avail Output When asserted, vidctl_vid_code is valid.
vidctl_avs_status Output When asserted., it indicates that the SmartVID feature is enabled.
vidctl_vid_code[5:0] Output 6-bit VID code from the SmartVID controller.
vidctl_temp_code[9:0] Output 10-bit temperature code from the SmartVID controller.
vidctl_temp_code_valid Output When asserted, the vidctl_temp_code value is valid.

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