SmartVID Controller IP Core User Guide

ID 683770
Date 5/08/2017

6. SmartVID Controller Reference Design

The SmartVID Controller reference design provides you an overview of the SmartVID controller system.
Figure 4. SmartVID Controller System with Arria 10 DeviceThe figure below shows the system-level block diagram of the SmartVID controller with the interfacing sub-systems within an Arria 10 device.

The SmartVID controller reference design contains the following components:
  • Reset synchronizer
  • Voltage regulator
    • Designed to remap the VID code from the SmartVID controller IP core to the corresponding voltage code of the targeted voltage regulator.
  • Temperature sensor
  • JTAG block
    • The reference design uses an IOPLL to generate the required 125 MHz and 25 MHz clocks. These clocks can also be supplied by a customer design if the reference design is used as a template to add the SmartVID feature.

Did you find the information on this page useful?

Characters remaining:

Feedback Message