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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
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4.3. Getting Started
You can instantiate the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series devices from IP Catalog in Quartus® Prime software. Altera provides an integrated parameter editor that allows you to customize this IP to support a wide variety of applications.
This IP is located in Libraries > Basic Functions > I/O of the IP catalog.