PHY Lite for Parallel Interfaces FPGA IP User Guide

ID 683716
Date 1/13/2025
Public

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Document Table of Contents

1.2. Features

Features of the PHY Lite for Parallel Interfaces FPGA IPs:

  • Support interface frequency range of 150 MHz to 1250 MHz (for Agilex™ 5 and Agilex™ 7 M-Series and devices) or 100 MHz to 1200 MHz (for Agilex™ 7 F-Series, Agilex™ 7 I-Series, and older devices).
  • Support input, output, and bidirectional data channels.
  • Support the DQS gating and ungating circuitry for strobe-based interfaces.
  • Support output delays through interpolator.
  • Support dynamic on-chip termination (OCT) control.
  • Support quarter-rate, half-rate, and full-rate mode of the interface clock conversions.
  • Support input, output, and read enable, strobe enable, and OCT enable paths.
  • Support single and double data rates (SDR and DDR) at the I/Os.
  • Support the PHY clock tree.
  • Support dynamically reconfigurable delay chains using the Avalon® memory-mapped interface.
  • Support process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
    Note: For Stratix® 10, Arria® 10, and Cyclone® 10 GX devices, you can set the non-PVT compensated component of the input delay through Quartus Settings File (.qsf) assignment in the Quartus® Prime software.

Table 1.  Key Features of PHY Lite for Parallel Interfaces FPGA IP
Family Cyclone® 10 GX Arria® 10 Stratix® 10 Agilex™ 7 F/I-Series Agilex™ 7 M-Series Agilex™ 5 D/E-Series
I/O Count 48 per bank 48 per sub-bank 96 per bank
Max # of groups 18 4 8
Structure Each Group must fit within 1 IO48 bank IP must fit within 1 IO48 sub-bank IP must fit within 1 IO96 bank
Interface frequency range 100 – 1200 MHz 150 – 1250 MHz
Core clock rate Selectable. The parameter clock rate of user logic allows you to choose (quarter, half, or full rate).

Not Selectable. Clock rate is auto-calculated.

Data configuration Single-ended/ Differential Single-ended only Single-ended/ Differential
Reserved pins No Strobe only Strobe and RZQ
Auto pin assignment No Yes (data, strobe, and reference clock) Yes (data, strobe, and RZQ)
I/O Standard

SSTL-12

SSTL-125

SSTL-135

SSTL-15

SSTL-15 Class I

SSTL-15 Class II

SSTL-18 Class I

SSTL-18 Class II

1.2-V-HSTL Class I

1.2-V-HSTL Class II

1.5-V-HSTL Class I

1.5-V-HSTL Class II

1.8-V-HSTL Class I

1.8-V-HSTL Class II

1.2-V POD

1.2-V

1.5-V

1.8-V

SSTL-12

1.2-V POD

SSTL-12

1.2-V POD

1.1-V POD

1.2-V HSTL

1.2-V HSUL

1.1-V LVSTL

1.05-V LVSTL
Auto generate address register map No Yes
Resolution (based on VCO freq.)

6.5104 - 13.0208 ps (output)

3.2522 - 6.5104 ps (input)

6.25 - 13.0208 ps (output)

6.25 - 13.0208 ps (input)

Delay range (based on VCO clock)

6.5104 - 130.208 ps @1200 MHz (output)

0 - 1663.4 ps @1200 MHz (input)

9.7656 - 625 ps @100 MHz (output)

0 - 2495.1 ps @100 MHz (input)

0 - 12.8 ns @1250 MHz (output)

0 - 12.8/24.0 ns @1250 MHz (input * )

0 - 26.67 ns @150 MHz (output)

0 - 26.67/50.00 ns @150 MHz (input * )
* Agilex™ 7 M-Series and Agilex™ 5 D/E-Series input RcvEn/read_enable_offset.