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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
3.2.2.2. Dynamic Reconfigurable Delays
Configurable Settings | Width | Description | Unit | Granularity |
---|---|---|---|---|
TxDqDelay | 11 | Output delay for data and strobe | 1/128 of VCO cycle | per pin |
RxDqsNDelayPi | 7 | Phase shift in negative edge of DQS | 1/128 of VCO cycle | per pin |
RxDqsPDelayPi | 7 | Phase shift in positive edge of DQS | 1/128 of VCO cycle | per pin |
RxRcvEnPiRank0 | 11 | RcvEn delay | 1/128 of VCO cycle | per nibble |
DqsSenseAmpDelay | 5 | DQS sense amplifier delay | PHY clock cycle | per nibble |
DqSenseAmpDuration | 4 | DQ sense amplifier duration | PHY clock cycle | per nibble |
DqSenseAmpDelay | 5 | DQ sense amplifier delay | PHY clock cycle | per nibble |
DqOdtDuration | 4 | DQ ODT duration | PHY clock cycle | per nibble |
DqOdtDelay | 5 | DQ ODT delay | PHY clock cycle | per nibble |
DqsOdtDuration | 4 | DQS ODT duration | PHY clock cycle | per nibble |
DqsOdtDelay | 5 | DQS ODT delay | PHY clock cycle | per nibble |
read_enable_offset | 4 | Delay before reading from the RX FIFO | PHY clock cycle | per lane |
RxDataVrefL | 9 | I/O reference voltage lower nibble | 1/512 of VCCN | per nibble |
RxDataVrefU | 9 | I/O reference voltage upper nibble | 1/512 of VCCN | per nibble |
TrainReset | 1 | Resets the training to clear non-permanent states - self clearing. Internal to the I/O lane and resets stateful logic on the read and write paths. | — | per lane |
RLTrainingMode | 1 | Enables read leveling training mode | — | per lane |
DataTrainFeedback_N0 | 12 | Provides feedback for different training steps. In RL Training mode it is simply a counter. | — | per nibble |
D0DlyRange | 2 | Enable/Set delay line inside the RxDqD0 for matched Rx. 0: Disable, 1: 1 delay cell, 2: 2 delay cells, 3: 3 delay cells. | — | common for all data pins |
For differential data, program the output delay settings for both pins in a differential pair, and the input settings only for the even pin.
Before adjusting any delays with dynamic reconfiguration, set the InternalClocksOn and reset the training. After calibration, set InternalClocksOn back to zero to save power. Follow these steps:
- Set InternalClocksOn = 1.
- Apply Train Reset by setting TrainReset from 0 to 1 and back to 0.
- Perform calibration.
- Set InternalClocksOn = 0.
If a PHY Lite group occupies two I/O lanes (for example, using a x16 DQS tree), expect additional delay on DQS over the PVT drift due to the longer DQS path.
Use the D0DlyRange register to shift out the DQ data so that the left edge of the data eye can be observed during DQS sweeps. At the maximum supported double data rate of 2500 MHz, 100ps is 0.25 UI; thus, setting the D0DlyRange register to 1 (1 delay cell) is usually sufficient.
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