PHY Lite for Parallel Interfaces FPGA IP User Guide

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ID 683716
Date 1/13/2025
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices 3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices 4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices 5. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices 6. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices 7. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives 8. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices Top Level Interfaces 2.2.2. Dynamic Reconfiguration
2.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions 2.4.1.3. Maximum Number of DQ Data Pin Configurations
2.4.1.3. Maximum Number of DQ Data Pin Configurations x
2.4.1.3.1. Automatic and Manual Pin Placement 2.4.1.3.2. Single-Ended Pin Configurations 2.4.1.3.3. Differential Pin Configurations 2.4.1.3.4. Mixed Pin Configurations
2.5. Design Example x
2.5.1. Generate the Design Example 2.5.2. Verify Simulation Design Examples using Tester IP
2.5.1. Generate the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Design Example with Dynamic Reconfiguration
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generate the Synthesis Design Example without Dynamic Reconfiguration 2.5.1.1.2. Generate the Simulation Design Example Without Dynamic Reconfiguration 2.5.1.1.3. Run the Simulation Design Example Without Dynamic Reconfiguration
2.5.1.2. Design Example with Dynamic Reconfiguration x
2.5.1.2.1. Generate the Synthesis Design Example With Dynamic Reconfiguration 2.5.1.2.2. Generate the Simulation Design Example with Dynamic Reconfiguration 2.5.1.2.3. Run the Simulation Design Example Without Dynamic Reconfiguration
2.5.2. Verify Simulation Design Examples using Tester IP x
2.5.2.1. PHY Lite Interface 2.5.2.2. I/O Model 2.5.2.3. IOSSM Tester 2.5.2.4. Write Test 2.5.2.5. Read Test 2.5.2.6. Calbus Test
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces 3.2.2. Dynamic Reconfiguration 3.2.3. I/O Timing
3.2.1. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces x
3.2.1.1. Clocks 3.2.1.2. Output Path 3.2.1.3. Input Path
3.2.1.1. Clocks x
3.2.1.1.1. Clock Frequency Relationships
3.2.2. Dynamic Reconfiguration x
3.2.2.1. Calibration IP 3.2.2.2. Dynamic Reconfigurable Delays 3.2.2.3. Register Map
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.5. Design Guidelines x
3.5.1. DQS Trees 3.5.2. Pin Placement Restrictions
3.6. Design Example x
3.6.1. Generating the Design Example 3.6.2. Verifying Simulation Design Examples using Tester IP
3.6.1. Generating the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generating the Synthesis Design Example 3.6.1.1.2. Generating the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Generating the Synthesis Design Example 3.6.1.2.2. Generating the Simulation Design Example
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Agilex™ 7 F-Series and I-Series I/O Sub-bank Interconnects 4.2.2. Agilex™ 7 F-Series and I-Series Input DQS/Strobe Tree 4.2.3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces 4.2.4. Dynamic Reconfiguration 4.2.5. I/O Timing
4.2.3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces x
4.2.3.1. Clocks 4.2.3.2. Output Path 4.2.3.3. Input Path
4.2.3.1. Clocks x
4.2.3.1.1. Clock Frequency Relationships
4.2.4. Dynamic Reconfiguration x
4.2.4.1. Connectivity 4.2.4.2. Reconfiguration Features and Register Addressing 4.2.4.3. Dynamic Reconfiguration Guidelines
4.2.4.2. Reconfiguration Features and Register Addressing x
4.2.4.2.1. Control Registers Addresses 4.2.4.2.2. Control Registers
4.2.4.3. Dynamic Reconfiguration Guidelines x
4.2.4.3.1. Strobe Enable Window Calibration 4.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 4.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset
4.6. Design Example x
4.6.1. Generating the Design Example
4.6.1. Generating the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generating the Synthesis Design Example 4.6.1.1.2. Generating the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Generating the Synthesis Design Example 4.6.1.2.2. Generating the Simulation Design Example
5. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices Control Registers Addresses 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces FPGA IP to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generating the Design Example
5.6.1. Generating the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generating the Hardware Design Example 5.6.1.1.2. Generating the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
6. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices x
6.1. Release Information 6.2. Functional Description 6.3. Getting Started 6.4. I/O Standards 6.5. Design Guidelines 6.6. Design Example 6.7. Application Specific Design Example
6.2. Functional Description x
6.2.1. Top Level Interfaces 6.2.2. Clocks 6.2.3. Output Path 6.2.4. Input Path 6.2.5. Dynamic Reconfiguration
6.2.2. Clocks x
6.2.2.1. Clock Frequency Relationships
6.2.3. Output Path x
6.2.3.1. Output Path Data Alignment
6.2.4. Input Path x
6.2.4.1. Input Path Data Alignment
6.2.5. Dynamic Reconfiguration x
6.2.5.1. RTL Connectivity 6.2.5.2. Address Lookup 6.2.5.3. Reconfiguration Features and Register Addressing 6.2.5.4. Calibration Guidelines
6.2.5.1. RTL Connectivity x
6.2.5.1.1. Daisy Chain
6.2.5.2. Address Lookup x
6.2.5.2.1. Strobes 6.2.5.2.2. Parameter Table Examples
6.2.5.3. Reconfiguration Features and Register Addressing x
6.2.5.3.1. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Address Registers 6.2.5.3.2. Control Registers Description
6.2.5.4. Calibration Guidelines x
6.2.5.4.1. Strobe Enable Window Calibration 6.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
6.3. Getting Started x
6.3.1. Parameter Settings 6.3.2. Signals
6.3.1. Parameter Settings x
6.3.1.1. Read Latency 6.3.1.2. Write Latency
6.3.2. Signals x
6.3.2.1. Clock and Reset Interface Signals 6.3.2.2. Output Path Signals 6.3.2.3. Input Path Signals 6.3.2.4. Avalon Configuration Bus Interface Signals 6.3.2.5. Termination Signals
6.4. I/O Standards x
6.4.1. Input Buffer Reference Voltage (VREF) 6.4.2. On-Chip Termination (OCT)
6.4.1. Input Buffer Reference Voltage (VREF) x
6.4.1.1. Calibrated VREF Settings
6.4.2. On-Chip Termination (OCT) x
6.4.2.1. RZQ_GROUP Assignment 6.4.2.2. Manual Insertion of OCT Block
6.5. Design Guidelines x
6.5.1. Guidelines: Group Pin Placement 6.5.2. Reference Clock 6.5.3. Reset 6.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 6.5.5. Dynamic Reconfiguration 6.5.6. Timing
6.5.6. Timing x
6.5.6.1. Timing Components 6.5.6.2. Timing Constraints and Files 6.5.6.3. Timing Analysis 6.5.6.4. Timing Closure Guidelines
6.5.6.2. Timing Constraints and Files x
6.5.6.2.1. <variation_name>.sdc 6.5.6.2.2. <variation_name>_parameter.tcl 6.5.6.2.3. <variation_name>_ip_parameters.tcl 6.5.6.2.4. <variation_name>_pin_map.tcl 6.5.6.2.5. <variation_name>_report_timing.tcl 6.5.6.2.6. <variation_name>_report_timing_core.tcl
6.5.6.4. Timing Closure Guidelines x
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration 6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 6.5.6.4.5. I/O Timing Violation 6.5.6.4.6. Internal FPGA Path Timing Violation
6.6. Design Example x
6.6.1. Generating the Design Example
6.6.1. Generating the Design Example x
6.6.1.1. Design Example without Dynamic Reconfiguration 6.6.1.2. Dynamic Reconfiguration Design Examples
6.6.1.1. Design Example without Dynamic Reconfiguration x
6.6.1.1.1. Generating the Hardware Design Example 6.6.1.1.2. Generating the Simulation Design Example
6.6.1.2. Dynamic Reconfiguration Design Examples x
6.6.1.2.1. Dynamic Reconfiguration with Debug Kit 6.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
6.7. Application Specific Design Example x
6.7.1. Implementation using the PHY Lite for Parallel Interfaces FPGA IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 D-Series and E-Series Devices
3. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide

8. Document Revision History for the PHY Lite for Parallel Interfaces FPGA IP User Guide

Document Version Quartus® Prime Version Changes
2025.01.13 24.3.1
  • Added Agilex™ 5 D-Series support throughout.
  • Applied Altera branding throughout.
  • In the About the PHY Lite for Parallel Interfaces IP chapter:
    • In the Features topic, added the Key Features of PHY Lite for Parallel Interfaces FPGA IP table.
  • In the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 5 D-Series and E-Series Devices chapter:
    • Added D0DlyRange to the table in the Dynamic Reconfigurable Delays topic.
    • In the Parameter Settings topic, added the RX Equalization parameter to the table.
    • In the Input Path topic, modified the first column heading in the Settings for DQ/DQS ODT/SA Delays table. Removed the associated footnote. Added a statement about half-rate and full-rate support.
    • Added a step 10 to the Pin Placement Restrictions topic.
    • Removed VCS from the table of supported simulators in the Run the Simulation Design Example Without Dynamic Reconfiguration topic.
    • Modified the last paragraph in the Dynamic Reconfiguration topic.
    • In the Dynamic Reconfigurable Delays topic, added four rows to the bottom of the table. Modified the TrainReset description. Added two sentences to the bottom of the topic.
    • In the Clock and Reset Interface Signals topic, modified the reset_n description in the table.
  • In the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 M-Series Devices chapter:
    • Added D0DlyRange to the table in the Dynamic Reconfigurable Delays topic.
    • In the Parameter Settings topic, added the RX Equalization parameter to the table.
    • In the Input Path topic, modified the first column heading in the Settings for DQ/DQS ODT/SA Delays table. Removed the associated footnote. Added a statement about half-rate and full-rate support.
    • Added a step 10 to the Pin Placement Restrictions topic.
    • Modified the last paragraph in the Dynamic Reconfiguration topic.
    • In the Dynamic Reconfigurable Delays topic, added four rows to the bottom of the table. Modified the TrainReset description. Added two sentences to the bottom of the topic.
    • In the Clock and Reset Interface Signals topic, modified the reset_n description in the table.
  • In the PHY Lite for Parallel Interfaces Intel FPGA IP for Agilex 7 F-Series and I-Series Devices chapter:
    • In the RZQ_GROUP Assignment topic, added a note to step 3.
    • In the RZQ_GROUP Assignment topic, modified the example qsf file in step 4.
  • In the PHY Lite for Parallel Interfaces Intel FPGA IP for Stratix 10 Devices chapter:
    • In the RZQ_GROUP Assignment topic, added a note to step 4.
    • In the RZQ_GROUP Assignment topic, modified the example qsf file in step 5.
    • Modified the Reference Clock topic.
  • In the PHY Lite for Parallel Interfaces Intel FPGA IP for Arria 10 and Cyclone 10 GX Devices chapter:
    • In the RZQ_GROUP Assignment topic, added a note to step 4.
    • In the RZQ_GROUP Assignment topic, modified the example qsf file in step 5.
    • Modified the Reference Clock topic.
2024.07.15 24.1 Added a note to step 3 in the RZQ_GROUP Assignment topic of the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices chapter.
2024.04.01 24.1
  • Added the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 5 E-Series Devices chapter.
  • Updated the sub-bank in the Agilex™ 7 F-Series and I-Series I/O Sub-bank Interconnects topic with additional diagrams.
  • Added a note in the Guidelines: Group Pin Placement topic of the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices chapter.
2024.01.12 23.4
  • Updated the Allowed values for read_enable_offset based on RcvEn coarde delay table.
  • Updated parameters in the Address Register Map table.
  • Added statements in the Dynamic Reconfigurable Delays topic about setting the InternalClocksOn bit and performing train reset, and a link to the Input Path Signals table.
  • Added a statement in the Guidelines: Group Pin Placement topic under the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 F-Series and I-Series Devices chapter about potential design failure.
  • Added a Worst Case Losses table under the I/O Timing topic of the PHY Lite for Parallel Interfaces FPGA IP for Agilex™ 7 M-Series Devices chapter.
  • Added examples about quarter rate and half rate modes in the Agilex™ 7 F-Series and I-Series Input DQS/Strobe Tree topic.
  • Updated the Pin Placement Restrictions section to add a note about avoiding overlapping of base addresses and information about ODT Rotation.
  • Added a note about avoiding overlapping of base addresses in the Parameter Settings topic.
  • Updated the IP names throughout the document to PHY Lite for Parallel Interfaces FPGA IP.
  • Updated the figure showing the M-Series FPGA I/O bank structure.
2023.08.02 23.2
  • Removed the note about restricted support for M-Series FPGAs.
  • Added rzq signal in the Clock and Reset Interface Signals table for the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for M-Series.
  • Updated the RZQ value for 1.2-V HSTL in the I/O Standards and Termination Values for Agilex™ 7 M-Series Devices table.
  • Added the following sub-bank ordering diagrams:
    • Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGF022 and AGF027 Devices, Package R31C
    • Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGF022 and AGF027 Devices, Package R31C
    • Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R29A
    • Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R29A
    • Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI027 Devices, Package R29B
    • Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI027 Devices, Package R29B
    • Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31A
    • Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31A
    • Sub-bank Ordering with ID in Top I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31B
    • Sub-bank Ordering with ID in Bottom I/O Row in Agilex™ 7 AGI022 and AGI027 Devices, Package R31B
  • Updated quarter core clock rate and added half and full core clock rates in the following tables for PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for F-Series and I-Series.
    • PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for F-Series and I-Series Supported Interface Frequency
    • Maximum Write Latency
  • Updated the description in the Dynamic Reconfiguration Guidelines section.
  • Updated the Strobe Enable Phase [9:0] incremental delay description in the Control Register Bit Description for PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for F-Series and I-Series.
  • Updated the description, dqs_clean Timing Diagram, and Adding Extra Dummy Pulses to Return PHY to Normal State diagram in the Strobe Enable Window Calibration sections for the following IPs:
    • PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for F-Series and I-Series
    • PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP
    • PHY Lite for Parallel Interfaces Arria® 10 FPGA IP and PHY Lite for Parallel Interfaces Cyclone® 10 GX FPGA IP
  • Made editorial updates throughout the document.
2023.04.10 23.1
  • Added information about Agilex™ 7 (F-Series, I-Series, and M-Series) in Device Family Support section.
  • Added PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for M-Series section.
  • Updated the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP for F-Series and I-Series section.
    • Added link to External Memory Interfaces Agilex™ 7 FPGA IP User Guide.
    • Added information about PHY Lite for Parallel Interfaces instances for Agilex™ 7 FPGA IP for F-Series and I-Series in I/O Standards.
    • Updated the range in Input DQ/DQS Delay Chains Maximum Values section.
2022.06.21 22.2
  • Removed Output Path Data Alignment and Input Path Data Alignment sections.
  • Removed information about PHY Lite for Parallel Interfaces IPs and the External Memory Interface IPs from Reconfiguration Features and Register Addressing section.
  • Added KDB link in Generate the Simulation Design Example section.
  • Added information to use +define+EMIF_DISABLE_CAL_OPTIMIZATIONS in Generate the Simulation Design Example section.
2021.12.13 21.4
  • Updated the About the PHY Lite for Parallel Interfaces IP section.
  • Updated the Intel Agilex I/O Sub-bank Interconnects section:
    • Updated the figure Sub-bank Ordering with ID in Top I/O Row in Intel Agilex AGF012 and AGF014, Package R24B.
    • Updated the figure Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex AGF012 and AGF014, Package R24B.
    • Updated the figure Sub-bank Ordering with ID in Top I/O Row in Intel Agilex AGF014, Package R24C.
    • Updated the figure Sub-bank Ordering with ID in Bottom I/O Row in Intel Agilex AGF014, Package R24C.
  • Updated the Intel Agilex Input DQS/Strobe Tree section:
    • Added the figure Pin Placement Example.
    • Updated the column header of the Pins Usable as Read Capture Clock / Strobe Pair table.
  • Updated the PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Top Level Interfaces section.
  • Updated the Dynamic Reconfiguration section:
    • Updated the Input DQ/DQS Delay Chains Maximum Values section.
  • Added a footnote on Values parameter in PHY Lite for Parallel Interfaces IP Parameter Settings table recommending to select based on the design, ideally through analog simulation using FPGA IBIS models and specific board.
  • Added a note on choosing the VREF range for the design using analog simulation in the Input Buffer Reference Voltage (VREF) and Input Buffer Reference Voltage (VREF) sections.
  • Added the figure High-Level View of the Synthesis Design Example with One Group.
  • Added related information in Calibration Guidelines section.
2021.09.01 21.1 Removed unsupported VREF modes from the VREF_MODE Description table for the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP: VCCIO_45, VCCIO_50, VCCIO_55, VCCIO_65, VCCIO_70, VCCIO_75.
2021.07.16 21.1
  • Updated the figure showing the I/O bank structure to improve clarity and to remove 3 V I/O.
  • Updated the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP v21.0.0 as follows:
    • Restructured the About the PHY Lite for Parallel Interfaces IP section.
    • Updated the column header of the Pins Usable as Read Capture Clock / Strobe Pair table.
    • Updated the Output Path section.
    • Added description for the Example Output for Quarter Rate DDR diagram.
    • Updated the Dynamic Reconfiguration Guidelines section.
    • Updated the Strobe Enable Window Calibration section.
    • Added the Input DQ/DQS Delay Chains Maximum Values section.
    • Added the I/O Timing section.
    • Updated the values for Capture strobe phase shift and Strobe configuration in the PHY Lite for Parallel Interfaces IP Parameter Settings table.
    • Updated the Input Buffer Reference Voltage (VREF) section.
      • Updated the VREF range selection via QSF for POD 1.2 V assignment command.
      • Added support for Calibrated VREF via dynamic reconfiguration.
      • Added DDR4_CAL and DDR4_CAL_RANGE2 VREF modes in the VREF_MODE Description table.
  • Updated the PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP as follows:
    • Updated the Strobe Enable Window Calibration section.
    • Updated the Dynamic Reconfiguration section.
  • Updated the Strobe Enable Window Calibration section for the PHY Lite for Parallel Interfaces Arria® 10 FPGA IP and PHY Lite for Parallel Interfaces Cyclone® 10 GX FPGA IP.
  • Removed references to the NCSim simulator.
  • Updated the topic listing the document archives to correct the topic title and the titles of the archived documents from Quartus® Prime versions 18.0 through 20.3.
2021.02.04 20.4

Updated the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP v20.3.0 as follows:

  • Updated the I/O resource and added support for dynamically reconfigurable delay chains using Avalon® memory-mapped interface for Agilex™ 7 devices in the Features section.
  • Updated the Agilex™ 7 I/O Sub-bank Interconnects section.
    • Stated that each sub-bank is labeled with ID number to facilitate pin placement.
    • Updated figure titles and added ID numbers in the diagrams.
  • Updated the Pins Usable as Read Capture Clock / Strobe Pair table.
  • Updated the maximum frequency for speed grade –2 and –3 in the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP Supported Interface Frequency table.
  • Added the Dynamic Reconfiguration section.
  • Updated the PHY Lite for Parallel Interfaces IP Parameter Settings table.
    • Updated values for Clock rate of user logic, Use dynamic reconfiguration, and Pin width.
    • Added the Pin Placement section.
    • Removed the Expose termination ports parameter.
    • Removed the Group <x> Placement Settings section.
  • Removed the Termination Signals and Manual Insertion of OCT Block sections.
  • Updated the steps to set RZQ pin locations in the RZQ_GROUP Assignment section.
  • Updated the Guidelines: Group Pin Placement section.
    • Updated the guidelines for group pin placement.
    • Updated the Pin Index Mapping table.
    • Added guidelines and example for automatic and manual pin placement.
    • Removed the Example of Occupied Data Pins for a Single Group Using Automatic Pin Placement and Example of Occupied Data Pins for a Single Group Using Manual Pin Placement diagrams.
  • Added command codes in the Reference Clock section.
  • Added the Generate the Design Example section. Included Generate the Simulation Design Example as a sub section.

Updated the Guidelines: Group Pin Placement sections for the following IPs:

  • PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP
  • PHY Lite for Parallel Interfaces Arria® 10 FPGA IP
  • PHY Lite for Parallel Interfaces Cyclone® 10 GX FPGA IP
Document Version Quartus® Prime Version Changes
2020.11.13 20.3
  • Updated the figure showing the I/O bank structure to add the pin naming orientation.
  • Repaired multiple broken links and descriptions throughout the document.
2020.10.19 20.3
  • Added information about PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP v20.3.0 support in Agilex™ 7 devices.
  • Restructured the user guide to separate the information into specific devices.
2020.06.30 20.2 Updated the Stratix® 10 I/O Bank Structure figure showing the I/O bank structure:
  • Added I/O bank structure for Stratix® 10 GX 10M device.
  • For I/O banks figure of other Stratix® 10 devices:
    • Marked only bank 3A as SDM shared LVDS I/O.
    • Marked HPS shared LVDS I/Os.
    • Added 3 V I/O banks 7A, 7B, and 7C.
Document Version Quartus® Prime Version IP Version Changes
2020.02.24 19.3 19.1
  • Added Why is the read data value incorrect for the DQS input delay when using the Dynamic Reconfiguration mode in the Arria® 10 PHYLite IP? KDB link to the Dynamic Reconfiguration topic.
  • Editorial updates for the Output Path — Write Latency 2 and Input Path ─ Read Latency 7 figures.
  • Updated dqs_enable signals in the Input Path figure to match signal names in Blocks in Data, Strobe, and Read Enable Paths table.
  • Removed redundant signal description for avl_writedata in the Avalon Memory-Mapped Master Interface Signals table.
  • Rebranded Avalon-MM to Avalon Memory-Mapped Interface.
2019.12.16 19.3 19.1
  • Updated note and related information link on using .sdc file in encrypted IOPLL Intel FPGA IP instances in the Reference Clock topic.
2019.11.07 19.3 19.1
  • Added the following topics:
    • Release Information
    • Timing Closure: Input Strobe Setup and Hold Delay Constraints
    • Timing Closure: Output Strobe Setup and Hold Delay Constraints
  • Added KDB link Why does the PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP cannot be assigned to Bank 3A or 3D when using the Stratix® 10 1ST040* device? to Functional Description chapter.
  • Added KDB link Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PHYLITE_GROUP(s)). to Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank chapter.
  • Added KDB link Warning: Failed to find atom information in IOPLL SDC: ERROR: Cannot access ENUM_IOPLL_FEEDBACK data of the encrypted atom node 111916. This operation involves an encrypted atom node. Use the BOOL_ENCRYPTED test to avoid such nodes and the error. to Reference Clock topic.
2019.04.04 19.1 19.1
  • Added Can the Arria® 10 and Cyclone® 10 GX I/O PLL have a VCO frequency below the minimum value shown in the device datasheets? KDB link in Clocks, Clock Frequency Relationships, and Parameter Settings sections.
2019.04.01 19.1 19.1
  • Added new parameter Reference clock I/O configuration in PHY Lite for Parallel Interfaces IP Core Parameter Settings table.
  • Removed information on manual assignment for reference clock I/O standards in the I/O Standards chapter.
2019.01.09 18.1 18.1 Added estimation time for a delay register value to change in Reconfiguration Features and Register Addressing.
2018.09.21 18.1 18.1
  • Clarified the definition for full, half, and quarter core clock rate in PHY Lite for Parallel Interfaces Supported Interface Frequency tables.
  • Added legend and updated Input Path figure to show each path and distinguish internal and external signals.
  • Updated description for data, strobe, and read and strobe enable paths in Blocks in Data, Strobe, and Read and Strobe Enable Paths table.
  • Updated read operation description in Read Operation Sequence table.
  • Updated Input Path Waveform, Output Path - Write Latency 0, and Output Path - Write Latency 3 figures.
  • Updated description in Input Path Signals table.
  • Added a note to rdata_en signal in Input Path Signals to describe when user should assert the signal when using PHY Lite for Parallel Interfaces IP as a receiver.
  • Clarified that only when External Memory Interface with Debug Component IP cores exists in the design with PHY Lite for Parallel Interfaces, the First PHYLite Instance in the Avalon Chain parameter should be disabled.
  • Added new parameter Fast simulation model in PHY Lite for Parallel Interfaces table.
  • Updated RZQ_GROUP Assignment topic with steps to manually assign user defined RZQ pin location.
  • Added the following topics:
    • Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table
    • Example of Accessing Dynamic Reconfiguration Control Registers using Avalon Controller
  • Removed description on supported devices for tables with information that supports all devices.
  • Clarified that PHY Lite for Parallel Interfaces in Arria® 10 and Cyclone® 10 GX devices do not support exposing additional output clocks if the VCO frequency is lower than 600 MHz in PHY Lite for Parallel Interfaces IP Core Parameter Settings table.
  • Added pll_extra_clock[0..3] and pll_locked signals in Clock and Reset Interface Signals table.
  • Updated Output Path and Input Path block diagrams with parameters that impact the internal modules.
2018.06.06 18.0 18.0
  • Removed For Arria® 10 and Cyclone® 10 GX devices, this value is for DQS output strobe. For Stratix® 10 devices, this value is for both DQ and DQS output strobe. note from Pin Output Delay feature in Control Register Description table.
2018.05.07 18.0 18.0
  • Changed VCCN voltage supply name to VCCIO.
  • Renamed Addressing section to Reconfiguration Features and Register Addressing.
  • Added Control Register Addresses tables for Stratix® 10, Arria® 10, and Cyclone® 10 GX devices.
  • Added Control Registers Description table for Stratix® 10, Arria® 10, and Cyclone® 10 GX devices.
  • Added How can the PHY Lite IP RZQ pin location be assigned? Knowledge Base Link in On-Chip Termination (OCT) section.
  • Added First PHYLite Instance in the Avalon Chain parameter to the PHY Lite for Parallel Interfaces IP Core Parameter Settings table.
  • Made Example Design Avalon Controller section as a sub-section in Dynamic Reconfiguration with Debug Kit Design Example.
  • Updated Avalon Controller Registers table with register descriptions.
  • Renamed Pin Output Phase feature to Pin Output Delay.
  • Updated the minimum interface frequency recommended for dynamic reconfiguration to 533 MHz in the PHY Lite for Parallel Interfaces IP Core Parameter Settings table.
  • Updated all IP names as per Intel rebranding.
Date Version Changes
November 2017 2017.11.30
  • Added information about Intel FPGA PHYLite for Parallel Interfaces in Stratix® 10 and Cyclone® 10 GX devices.
  • Added note to Reference Clock about using cascaded PLL as a reference clock in Arria® 10 devices and a link to the KDB.
  • Rebranded to Intel FPGA PHYLite for Parallel Interfaces IP core.
June 2017 2017.06.16
  • Added a note for the I/O Column for Arria 10 Devices figure.
  • Updated Top-Level Interface diagram.
  • Updated OCT section.
  • Updated Guidelines: Group Pin Placement section.
  • Updated the reference clock source in the Reference Clock section.
  • Added Reset section.
  • Added a note on Report DDR function in "<variation_name>_report_timing.tcl" section.
  • Updated Altera PHYLite for Parallel Interfaces IP Core Parameter Settings table.
    • Removed Use core PLL reference clock connection parameter.
    • Added description for outclk (Reserved) parameter.
    • Updated OCT enable size values and description.
    • Added new parameter: Expose termination ports.
  • Updated the description for ref_clk and interface_locked signals in the Clock and Reset Interface Signals table.
  • Updated the description for data_in and data_io signals in Input Path Signals table.
  • Rebranded as Intel.
February 2017 2017.02.24
  • Removed 30 and 40 Ohms termination values for SSTL-125, SSTL-135, and SSTL-15 I/O standards.
  • Added a footnote to I/O Standards table recommending to use I/O standards SSTL-15 Class I, SSTL-15 Class II, SSTL-18 Class I, SSTL-18 Class II, 1.2V HSTL Class I, 1.2V HSTL Class II, 1.5V HSTL Class I, 1.5V HSTL Class II, 1.8V HSTL Class I, and 1.8V HSTL Class II for interface frequency equal or less than 533 MHz and if input termination required.
  • Added a footnote to I/O Standards table recommending to use I/O standards SSTL-12, SSTL-125, SSTL-135, and SSTL-15 for interface frequency more than 533 MHz and if input termination required.
October 2016 2016.10.28
  • Added OCT section.
  • Clarified that output terminations can be calibrated and uncalibrated in I/O Standards table.
  • Added footnote to clarify that uncalibrated output terminations do not require RZQ pin in I/O Standard table.
  • Clarified ONFI device support is for synchronous mode only.
  • Updated Altera PHYLite for Parallel Interfaces IP Core supported Interface Frequency table.
  • Clarified that reference clock using differential I/O standards support LVDS input buffer only.
  • Updated I/O standards table with Valid Input Termination values.
  • Added new guidelines to Group Pin Placement section.
  • Updated Avalon Address for following features in the Address Map table:
    • Pin PVT Compensated Input Delay
    • Strobe PVT compensated input delay
    • Strobe enable phase
  • Added Altera PHYLite NAND Flash design example in Application Specific Design Example section.
  • Removed IP Migration for Arria V, Cyclone V, and Stratix V section.
May 2016 2016.05.02
  • Change External memory clock domain to Interface clock domain.
  • Removed VCO Frequency Multiplication Factor table.
  • Updated equation to calculate values for Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters.
  • Updated Address Map table with values to enable Avalon address and CSR address.
  • Added a note to show the location of the Altera PHYLite for Parallel Interfaces IP core in IP Catalog.
  • Updated values for OCT enable size parameter.
  • Added reference link to I/O Standards table in Data configuration parameter description.
  • Added VCO clock frequency parameter in Parameter Settings table.
  • Updated Minimum Read Latency and Maximum Write Latency tables.
  • Updated PHYLite_delay_calculations.xlsx file.
  • Added issp.tcl file description in Dynamic Reconfiguration with Debug Kit Design Example Generated Files table.
  • Updated steps to generate Dynamic Reconfiguration with Debug Kit design example.
  • Added functional description, simulation steps and result to Dynamic Reconfiguration with Configuration Control Module Design Example.
  • Added Altera PHYLite for Parallel Interfaces IP Core Document Archives section.
December 2015 2015.12.11
  • Changed Input Path Waveform figure label from "Intrinsic output delay at current in and out rates and frequency" to "Intrinsic input delay at current in and out rates and frequency".
November 2015 2015.11.02
  • Added Altera PHYLite for Parallel Interface IP core uses cases.
  • Clarified the condition for reference clock restriction in Reference Clock section.
  • Added description for <variation_name>_parameter.tcl, <variation_name>_report_timing.tcl, and <variation_name>_report_parameter_core.tcl files into Timing Constrains and Files section.
  • Provided example timing constraint command for increasing hold time uncertainty value.
  • Added footnote to clarified functionality for DQS A and DQS B signals.
  • Added new parameters in the Altera PHYLite for Parallel Interfaces IP Core Parameter Settings table:
    • Copy parameters from another group
    • Group
    • OCT enable size
    • Inter Symbol Interference of the Read Channel
    • Inter Symbol Interference of the Write Channel
    • Group <x> Dynamic Reconfiguration Timing Settings
  • Added new dynamic reconfiguration with debug kit hardware example design.
  • Added Write Latencies table in Parameter Settings.
  • Updated Read Latencies table.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12
  • Updated Avalon Address R/W from 3'h2 to 3'h4 for all features in Address Map table.
  • Added new parameter Use core PLL reference clock connection and Data configuration in Altera PHYLite for Parallel Interfaces IP Core Parameter Settings table.
  • Updated values in VCO Frequency Multiplication Factor table.
January 2015 2015.01.28 Updated related information link to Functional Description for External Memory Interfaces in Arria 10 Devices.
December, 2014 2014.12.30
  • Updated the name of the IP core from Altera PHYLite for Memory to Altera PHYLite for Parallel Interfaces.
  • Updated the maximum clock frequency from 800 MHz to 1333.333 MHz.
  • Clarified that to achieve timing closure at 800 MHz and above, you must use dynamic reconfiguration to calibrate the interface.
  • Added data_out_n/data_io_n signals to the Output Path Signals table.
  • Added data_in_n/data_io_n signals to the Input Path Signals table.
  • Updated data_out/data_io and data_in/data_io signals in the Input Path Signals and Output Path Signals tables.
  • Updated Parameter Settings table to include Group <x> Timing Settings information.
  • Updated Timing section to include Input Strobe Setup Delay Constrain and Input Strobe Hold Delay Constrain parameters information.

August, 2014

2014.08.18

  • Renamed the term megafunction to IP core.
  • Added information about output path data alignment, input path data alignment, OCT, I/O standards, placement restrictions, timing, dynamic reconfiguration.
  • Added the PHYLite_delay_calculations.xlsx file.
  • Replaced ALTERA_PHYLite_nand_flash_example_131a10.qar file with nand_flash_example_14.0a10.qar file.

November, 2013

2013.11.29

Initial release.

Level Two Title