Intel® Agilex™ Configuration User Guide

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ID 683673
Date 5/30/2022
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4.4. Guidance When Using Partial Reconfiguration (PR)

The PR Region Controller IP provides reset logic that ensures that the static region of the device and the PR personas do not interact during PR.

The Reset Release IP is only necessary to manage reset for full FPGA core configuration and subsequent full FPGA core reconfigurations. The Reset Release IP is not necessary to prevent interaction between the static and PR personas during the PR process. For more information about PR refer to the Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.

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