Intel® Agilex™ Configuration User Guide

ID 683673
Date 5/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash

Create a FLASH_CLK clock

Example below creates assigns QSPI flash clock pin (flash_dc1_ic0) to the flash clock.

create_generated_clock -name FLASH_CLK -source [get_ports {clk_50m_sysmax}] [get_ports {flash_dc1_io0}]

Set output delay for PFL II IP output pins

Example below sets the output delay for the QSPI flash data and chip select pins.

#flash_dc1_io1/3/4/5 = QSPI flash data pins, 
#flash_dc1_io2 = QSPI flash chip select pins
set flash_data_tracemax 0.250
set flash_data_tracemin 0.000
set flash_clk_tracemax 0.250
set flash_clk_tracemin 0.000
set flash_Tsu 2.700
set flash_Th 2.000
set flash_out_max_dly [expr $flash_data_tracemax + $flash_Tsu - $flash_clk_tracemin]
set flash_out_min_dly [expr $flash_data_tracemin - $flash_Th - $flash_clk_tracemax]

set_output_delay -add_delay -max \
-clock [get_clocks {FLASH_CLK}] $flash_out_max_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5 flash_dc1_io2}]

set_output_delay -add_delay -min \
-clock [get_clocks {FLASH_CLK}] $flash_out_min_dly [get_ports { flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5 flash_dc1_io2}]

Set input delay for input pins

Example below sets the input delay for the QSPI flash data.

set flash_tco_max 7.000
set flash_tco_min 1.000
set in_max_dly [expr $flash_data_tracemax + $flash_tco_max + $flash_clk_tracemax]
set in_min_dly [expr $flash_data_tracemin + $flash_tco_min + $flash_clk_tracemin]

set_input_delay -clock { FLASH_CLK } -max $in_max_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5}]
set_input_delay -clock { FLASH_CLK } -min $in_min_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5}]

Did you find the information on this page useful?

Characters remaining:

Feedback Message