Intel® Agilex™ Configuration User Guide

ID 683673
Date 5/30/2022
Public

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3.3. JTAG Configuration

JTAG-chain device programming is ideal during development. JTAG-chain device configuration uses the JTAG pins to configure the Intel® Agilex™ FPGA directly with the .sof/.rbf file. Configuration using the JTAG device chain allows faster development because it does not require you to program external flash memory. You can also use JTAG to reprogram if the image stored in quad SPI memory. You can also use the JTAG configuration scheme to reprogram the quad SPI memory if the quad SPI content is corrupted or invalid.

The Intel® Quartus® Prime software generates a .sof/.rbf file containing the FPGA design information. You can use the .sof/.rbf file with a JTAG programmer to configure the Intel® Agilex™ device. The Intel® FPGA Download Cable II and the Intel® FPGA Ethernet Cable both can support the VCCIO_SDM supply at 1.8 V. Alternatively, you can use the Jam* STAPL Format File (.jam) or Jam* Byte Code File (.jbc) for JTAG configuration. After the JTAG configuration, the host executes CONFIG_STATUS SDM command to ensure the configuration is successful.

Intel® Agilex™ devices automatically compress the configuration bitstream. You cannot disable compression in Intel® Agilex™ devices.

Table 36.   Intel® Agilex™ Configuration Data Width, Clock Rates, and Data RatesMbps is an abbreviation for Megabits per second.
Mode Data Width (bits) Max Clock Rate Max Data Rate MSEL[2:0]
Passive JTAG 1 30 MHz 30 Mbps 3'b111
Note: The JTAG port has the highest priority and overrides the MSEL pin settings. Consequently, you can configure the Intel® Agilex™ device over JTAG even if the MSEL pin specify a different configuration scheme unless you disabled JTAG for security reasons.
Table 37.  Power Rails for the Intel® Agilex™ Device Configuration Pins
Configuration Function Pin Type Direction Powered by
TCK Fixed Input VCCIO_SDM
TDI 12 Fixed Input VCCIO_SDM
TMS 12 Fixed Input VCCIO_SDM
TDO 12 Fixed Output VCCIO_SDM
nSTATUS SDM I/O Output VCCIO_SDM
nCONFIG SDM I/O Input VCCIO_SDM
MSEL[2:0] SDM I/O Input VCCIO_SDM
12 The JTAG pins can access the HPS JTAG chain in Intel® Agilex™ SoC devices.

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