Intel® Agilex™ Configuration User Guide

ID 683673
Date 5/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1. Understanding the Reset Release IP Requirement

Intel® Agilex™ devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Device configuration proceeds in parallel with each Local Sector Manager (LSM) configuring its own sector. Consequently, FPGA registers and core logic do not exit reset at exactly the same time, as has always been the case in previous families.

The continual increases in clock frequency, device size, and design complexity now necessitate a reset strategy that considers the possible effects of slight differences in the release from reset. The Reset Release Intel FPGA IP holds a control circuit in reset until the device has fully entered user mode. The Reset Release FPGA IP generates an inverted version of the internal INIT_DONE signal, nINIT_DONE for use in your design.

After nINIT_DONE asserts (low), all logic is in user mode and operates normally. You can use the nINIT_DONE signal in one of the following ways:

  • To gate an external or internal reset.
  • To gate the reset input to the transceiver and I/O PLLs.
  • To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers.
  • To synchronously drive register reset input ports in your design.
Attention: If you use multiple Reset Release Intel FPGA IP instances in your design, the nINIT_DONE signals are driven directly from the same source in SDM.

Did you find the information on this page useful?

Characters remaining:

Feedback Message