AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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ID 683671
Date 6/12/2018
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Document Table of Contents x
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Updated for:
Intel® Quartus® Prime Design Suite 18.0
The Ultra Low Latency Ethernet 10G reference design demonstrates Low Latency 10G Ethernet solution for Intel® Stratix® 10 devices.

This Ethernet solution is developed using Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel® FPGA IP core and Intel® Stratix® 10 H-tile Transceiver Native PHY with small form-factor pluggable plus (SFP+) transceiver module. This reference design, which uses 10GBASE-R PHY with IEEE 1588v2 mode, is capable to achieve a lower round-trip latency, 171.0 nanoseconds (ns) compared to 10GBASE-R Ethernet design example for Intel® Stratix® 10 devices (246.5 ns).

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