AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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ID 683671
Date 6/12/2018
Public
Document Table of Contents
Document Table of Contents x
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Hardware and Software Requirements

The reference design requires and uses the following software and hardware tools:
  • Software:
    • Intel® Quartus® Prime Pro Edition software version 18.0
    • Platform Designer
    • System Console
    • ModelSim* -SE simulator version 10.6c
  • Hardware:
    • Intel® Stratix® 10 GX H-tile Transceiver Signal Integrity (SI) Development Board (1SG280HU2F50E2VGS1)
    • Intel® FPGA Download Cable
    • SFP+ optical transceiver module, which supports 10GBASE-R
    • Fiber optic loopback cable
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