AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

ID 683671
Date 6/12/2018

Clocking and Reset Scheme

Figure 2. Clocking and Reset SchemeThis figure shows the clocking and reset scheme for this reference design. In this design’s top level, there are two external clock sources, ref_clk_clk (644.53125 MHz) and csr_clk (125 MHz). There is one active-low and asynchronous master reset signal, master_reset_n in the top-level of this reference design. The master reset signal is used to reset all modules in the reference design.