AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
ID
683671
Date
6/12/2018
Public
Hardware Setup
Before you run the design, you need to set up the development board as shown in the following figures:
Figure 8. SFP+ External Loopback Hardware Test Setup
Figure 9. SFP+ External Loopback Hardware Test Setup in Lab