Interface Signals
| Signal | Direction | Width | Description |
|---|---|---|---|
| clk_clk | Input | 1 | Configuration clock for the Avalon® -MM interface and core logics. Frequency is 125 MHz. |
| ref_clk_clk | Input | 1 | Reference clock for the ATX PLL and fPLL. Frequency is 644.53125 MHz. |
| tx_xcvr_clk | Output | 1 | 322.265625 MHz clock for the TX datapath. This clock is output from tx_clkout of PHY. |
| rx_xcvr_clk | Output | 1 | 322.265625 MHz clock for the RX datapath. This clock is output from rx_clkout of PHY. |
| outclk_div1 | Output | 1 | 161.1328125 MHz clock for components such as address decoder, traffic controller, FIFO, and adapter. This clock is generated from fPLL. |
| tx_serial_clk | Output | 1 | The high-speed serial clock generated by the ATX PLL that drives the Native PHY. Frequency is 5.15625 GHz. |
| rx_cdr_refclk0 | Input | 1 | The reference clock source for PHY’s RX CDR PLL. This clock is sourced from ref_clk_clk. |
| master_reset_n | Input | 1 | Assert this asynchronous and active-low signal to reset the whole design example. |
| csr_rst_n | Input | 1 | Active-low reset signal for the Avalon® -MM interface. |
| tx_rst_n | Input | 1 | Active-low reset signal for the TX datapath. |
| rx_rst_n | Input | 1 | Active-low reset signal for the RX datapath. |
| Signal | Direction | Description |
|---|---|---|
| csr_write avl_mm_write |
Input | Assert this signal to request a write. |
| csr_read avl_mm_read |
Input | Assert this signal to request a read. |
| csr_address avl_mm_baddress |
Input | Use this bus to specify the register address you want to read from or write to. |
| csr_readdata avl_mm_readdata |
Output | Carries the data read from the specified register. |
| csr_writedata avl_mm_writedata |
Input | Carries the data to be written to the specified register. |
| csr_waitrequest avl_mm_waitrequest |
Output | Asserted when IP core is busy and not ready to accept any read or write request. |
| Signal | Direction | Width | Description |
|---|---|---|---|
| rx_serial_data | Input | 1 | RX serial input data to PHY. |
| tx_serial_data | Output | 1 | TX serial input data from PHY. |
| Signal | Direction | Width | Description |
|---|---|---|---|
| block_lock | Output | 1 | Asserted when the link synchronization is successful. |
| rx_ready_export | Output | 1 | Asserted when the RX channel is ready for data transmission. |
| tx_ready_export | Output | 1 | Asserted when the TX channel is ready for data transmission. |
| atx_pll_locked | Output | 1 | Asserted when the TX PLL is locked. |
| core_pll_locked | Output | 1 | Asserted when the fPLL is locked. |