AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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Date 6/12/2018
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Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Configuration Registers and Status Registers

Table 9.   System Register Map
Base Address Block
0x0000_0000 LL 10GbE Intel® FPGA IP core
0x0000_8000 L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP
0x0000_d400 RX SC FIFO
0x0000_d600 TX SC FIFO
0x0000_0C00 Traffic Controller
Table 10.  Traffic Controller Configuration Registers Map
Byte Offset Name Width R/W HW Reset Value Description
0x00 number_packet 32 RW 0x00 Used to specify the number of packets to be generated.
0x04 random_length 32 RW 0x00 Specifies the type of packet length.
  • Bit [0]—0 or 1
    • 0 = fixed length
    • 1 = random length
  • Bit [31:1]—Reserved
0x08 randam_payload 32 RW 0x00 Specifies the data pattern for the packet.
  • Bit [0]—0 or 1
    • 0 = incremental data pattern
    • 1 = random data pattern
  • Bit [31:1]—Reserved
0x14 source_addr0 32 RW 0x00 Used to specify 6-bytes source or destination MAC address.

source_addr0/destination_addr0 = last four bytes of the address

  • Bits [15:0] of source_ addr1/destination_addr1—first two bytes of the address
  • Bits [31:16] of source_ addr1/destination_addr1—unused
  • For example, if the source MAC address is 00-1C-23-17- 4A-CB, you get the following assignments:
    • source_addr0 = 0x17231C00
    • source_addr1 = 0x0000CB4A
0x18 source_addr1 32 RW 0x00
0x01C destination_addr0 32 RW 0x00
0x020 destination_addr1 32 RW 0x00
0x024 packet_tx_count 32 RO 0x00 This register keeps track the number of packets that the generator transmitted successfully. This register clears if the packet generation is triggered.
0x028 rand_seed0 32 RW 0x5EED0000
  • The lower 32 bits of the random seed.
  • Occupies bits 31:0 of the PBRS generator when you set the data pattern to random (Set random_payload register to 1).
0x02C rand_seed1 32 RW 0x5EED0001
  • The middle 32 bits of the random seed.
  • Occupies bits 63:32 of the PBRS generator when you set the data pattern to random (Set random_payload register to 1).
0x030 rand_seed2 32 RW 0x00025EED
  • The upper 32 bits of the random seed.
  • Occupies bits 91:64 of the PBRS generator when you set the data pattern to random (Set random_payload register to 1).
0x034 pkt_length 32 RW 0x00
  • Bits [13:0]—Specifies the fixed packet length and the valid values are between 24 to 9600 bytes. It is applicable only when you set the random_length register to 0.
  • Bit [31:14]—Reserved.
0x400 number_packet 32 RO 0x00 Total number of packets that the monitor expects to receive.
0x404 good_pkts 32 RO 0x00 Total number of received good packets.
0x408 bad_pkts 32 RO 0x00 Total number of received packets with errors.
0x40C byte_rx_count_0 32 RO 0x00
  • 64-bit counter that keeps track of the total number of bytes received.
  • byte_rx_count_0 represents the lower 32 bits.
  • byte_rx_count_1 represents the upper 32 bits.
  • Read byte_rx_count_0 followed by byte_rx_count_1 in the subsequent cycle to get an accurate count.
0x410 byte_rx_count_1 32 RO 0x00
0x414 cycle_rx_count_0 32 RO 0x00
  • 64-bit counter that keeps track of the total number of cycles the monitor takes to receive all packets.
  • cycle_rx_count_0 represents the lower 32 bits.
  • cycle_rx_count_1 represents the upper 32 bits.
  • Read cycle_rx_count_0 followed by cycle_rx_count_1 in the subsequent cycle to get an accurate count.
0x418 cycle_rx_count_1 32 RO 0x00
0x41C mon_csr 32 RW/RO 0x00
  • Bit 0—Set this bit to 1 to trigger packets reception. This bit clears after packet reception is started.
  • Bit 2—A value of 1 indicates that the packet monitor has received the total number of packets specified in the number_packet register.
  • Bit 3—A value of 1 indicates that the current packet received by monitor has CRC error.
  • Bits [9:4]—Receive error status. The behavior of rx_err signal in Low Latency Ethernet 10G MAC Intel® FPGA IP core is mapped to this register.
  • Bits [31:10]—Reserved
0x800 avalon_st_loopback_ena 32 RW 0x00 Bit 0 – Set this bit to 1 to enable loopback between Avalon® -ST TX interface and Avalon® -ST RX interface in traffic controller.
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