Design Components
| Component | Description |
|---|---|
| LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP core with the following configuration:
|
| PHY | The L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP configured for the 10GBASE-R protocol. The 10GBASE-R 1588 mode preset sets the PHY's TX FIFO MODE and RX FIFO MODE to Phase Compensation. |
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP core. Resets the transceiver. |
| Address decoder | Decodes the addresses of the components such as traffic controller, LL 10GbE MAC, and PHY. |
| Reset Synchronizer | Synchronizes the reset of all design components. |
| ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 10G transceiver. |
| Adapter | A dual clock FIFO adapter, which converts 32-bit Avalon® -ST interface of MAC to 64 bit. |
| FIFO | Avalon® Streaming ( Avalon® -ST) single-clock FIFO, which is used to buffer the RX and TX data between the MAC IP core and the client |
| Traffic Controller | The traffic controller consists of:
|