AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

ID 683671
Date 6/12/2018

Design Components

Table 1.  Design Components
Component Description

The Low Latency Ethernet 10G MAC Intel® FPGA IP core with the following configuration:

  • Speed: 10G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable 10GBASE-R register mode: Selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • TX and RX datapath Reset/Default To Enable: Selected
  • Use legacy XGMII Interface: Not selected
  • Use legacy Avalon Memory-Mapped Interface: Selected
  • Use legacy Ethernet 10G MAC Interfaces: Not selected
PHY The L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP configured for the 10GBASE-R protocol. The 10GBASE-R 1588 mode preset sets the PHY's TX FIFO MODE and RX FIFO MODE to Phase Compensation.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP core. Resets the transceiver.
Address decoder Decodes the addresses of the components such as traffic controller, LL 10GbE MAC, and PHY.
Reset Synchronizer Synchronizes the reset of all design components.
ATX PLL Generates a TX serial clock for the Intel® Stratix® 10 10G transceiver.
Adapter A dual clock FIFO adapter, which converts 32-bit Avalon® -ST interface of MAC to 64 bit.
FIFO Avalon® Streaming ( Avalon® -ST) single-clock FIFO, which is used to buffer the RX and TX data between the MAC IP core and the client
Traffic Controller The traffic controller consists of:
  • Traffic generator: Generates burst packets to the MAC for transmission.
  • Traffic monitor: Receives burst packets from MAC.