AN 903: Accelerating Timing Closure: in Intel® Quartus® Prime Pro Edition

ID 683664
Date 2/25/2021
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1.2. Step 2: Apply Compiler Optimization Techniques

Designs that utilize a very high percentage of FPGA device resources can cause resource congestion, resulting in lower fMAX and more complex timing closure.

The Compiler's Optimization Mode settings allow you specify the focus of Compiler efforts during synthesis. For example, you optimize synthesis for Area, or Routability when addressing resource congestion. You can experiment with combinations of these same Optimization Mode settings in the Intel® Quartus® Prime Design Space Explorer II. These settings and other manual techniques can help you to reduce congestion in highly utilized designs.

Timing Closure Problem

  • Designs with very high device resource utilization complicate timing closure.

Timing Closure Solutions