AN 903: Accelerating Timing Closure: in Intel® Quartus® Prime Pro Edition

ID 683664
Date 2/25/2021

1.3.1. Lock Down Clocks, RAMs, and DSPs

You can simplify timing closure by back-annotating satisfactory compilation results to lock down placement of large blocks related to Clocks, RAMs, and DSPs. Locking down large block placement can produce higher fMAX with less noise.

Locking down large blocks like RAMs and DSPs can be effective because these blocks have heavier connectivity than regular LABs, complicating movement during placement. When a seed produces good results from suitable RAM and DSP placement, you can capture that placement with back-annotation. Subsequent compiles can then benefit from the high quality RAM and DSP placement from the good seed. This technique does not significantly benefit designs with very few RAMs or DSPs.

Click Assignments > Back-Annotate Assignments to copy the device resource assignments from the last compilation to the .qsf for use in the next compilation. Select the back-annotation type in the Back-annotation type list.

Figure 18. Back-Annotate Assignments Dialog Box

Alternatively, you can run back-annotation with the following quartus_cdb executable.

quartus_cdb <design_name> --back_annotate [--dsp] [--ram] [--clock]
Note: The executable supports the additional [--dsp], [--ram], and [--clock] variables that the Back-Annotate Assignments dialog box does not yet support.