1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition
|Intel® Quartus® Prime Design Suite 19.3
The density and complexity of modern FPGA designs, that combine embedded systems, IP, and high-speed interfaces, present increasing challenges for timing closure. Late architectural changes and verification challenges can lead to time consuming design iterations.
This document summarizes three steps to accelerate timing closure using a verified and repeatable methodology in the Intel® Quartus® Prime Pro Edition software. This methodology includes initial RTL analysis and optimization, as well as automated techniques to minimize compilation time and reduce design complexity and iterations required for timing closure.
|Timing Closure Step
|Timing Closure Activity
|Step 1: Analyze and Optimize RTL
|Step 2: Apply Compiler Optimization
|Step 3: Preserve Satisfactory Results