1.1. Step 1: Analyze and Optimize Design RTL
Optimizing your design’s source code is typically the first and most effective technique for improving the quality of your results. The Intel® Quartus® Prime Design Assistant helps you to quickly correct basic design rule violations, and recommends RTL changes that simplify design optimization and timing closure.
Timing Closure Problems
- Excessive logic levels influences Fitter processing order, duration, and quality of results.
- High fan-out nets cause resource congestion and add additional tension on data paths, needlessly increasing the path criticality, and complicating timing closure. This tension is the attraction force pulling the path (and all paths that share that high fan-out signal) towards the high fan-out source.
Timing Closure Solutions
- Correct Design Assistant Violations—to quickly identify and correct basic design rule violations relevant to your design.
- Reduce Logic Levels—to ensure that all elements of the design can receive the same Fitter optimizations and to reduce compile times.
- Reduce High Fan-Out Nets—to reduce resource congestion and simplify timing closure.
"Design Rule Checking with Design Assistant," Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations
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