1.1.3. Reduce High Fan-Out Nets
In the following corner cases, you can additionally reduce congestion by making the following manual changes to your design RTL:
|Design Characteristic||Manual RTL Optimization|
|High fan-out nets that reach many hierarchies or physically far destinations||Specify the duplicate_hierarchy_depth assignment on the last register in a pipeline to manually duplicate high fan-out networks across hierarchies. Specify the duplicate_register assignment to duplicate registers during placement.|
|Designs with control signals to DSP or M20K memory blocks from combinational logic||Drive the control signal to the DSP or M20K memory from a register.|
Register Duplication Across Hierarchies
You can specify the duplicate_hierarchy_depth assignment on the last register in a pipeline to guide the creation of register duplication and fan-outs. The following figures illustrate the impact of the following duplicate_hierarchy_depth assignment:
set_instance_assignment -name duplicate_hierarchy_depth -to \ <register_name> <level_number>
- register_name—the last register in a chain that fans out to multiple hierarchies.
- level_number—the number of registers in the chain to duplicate.
set_instance_assignment –name DUPLICATE_HIERARCHY_DEPTH –to regZ M
set_instance_assignment –name DUPLICATE_HIERARCHY_DEPTH –to regZ 1
set_instance_assignment –name DUPLICATE_HIERARCHY_DEPTH –to regZ 3
By duplicating and pushing the registers down into the hierarchies, the design retains the same number of cycles to all the destinations, while greatly accelerating performance on these paths.
Register Duplication During Placement
Figure 11 shows a register with high fan-out to a widely spread area of the chip. By duplicating this register 50 times, you can reduce the distance between the register and the destinations that ultimately result in faster clock performance. Assigning duplicate_register allows the Compiler to leverage physical proximity to guide the placement of new registers feeding a subset of fan-outs.
Viewing Duplication Results
Following design synthesis, view duplication results in the Hierarchical Tree Duplication Summary report in the Synthesis folder of the Compilation Report. The report provides the following:
- Information on the registers that have the duplicate_hierarchy_depth assignment.
- Reason for the chain length that you can use as a starting point for further improvements with the assignment.
- Information about the individual registers in the chain that you can use to better understand the structure of the implemented duplicates.
The Fitter report also includes a section on registers that have the duplicate_register setting.
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