1. AN 899: Reducing Compile Time with Fast Preservation
|Intel® Quartus® Prime Design Suite 19.3|
Intel® Quartus® Prime Pro Edition allows you to preserve satisfactory compilation results for FPGA periphery or core logic design blocks, and then reuse the placement and routing of those blocks in subsequent compilations. You assign the hierarchical instance as a design partition, which you can then preserve and reuse following successful compilation.
Design Setup Requirements
The use of fast preservation requires one or more reserved core partitions, and a preserved .qdb functioning as the root partition. This design partitioning is similar to that required for the device periphery reuse or partial reconfiguration (PR) implementation flow. This tutorial includes a design example to demonstrate this setup.
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