AN 899: Reducing Compile Time with Fast Preservation

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ID 683493
Date 11/06/2019
Public

1. AN 899: Reducing Compile Time with Fast Preservation

Updated for:
Intel® Quartus® Prime Design Suite 19.3
This tutorial demonstrates how to use the fast preservation feature, along with design partitions, to reduce the overall compile time for a design.
The Fast Preserve option simplifies the logic of a preserved partition during compilation to only the interface logic between the partition boundary and the rest of the design, thereby reducing the compilation time required for that partition.
Preserve Timing Closed Partitions to Reduce Compile Times

Intel® Quartus® Prime Pro Edition allows you to preserve satisfactory compilation results for FPGA periphery or core logic design blocks, and then reuse the placement and routing of those blocks in subsequent compilations. You assign the hierarchical instance as a design partition, which you can then preserve and reuse following successful compilation.

Design Setup Requirements

The use of fast preservation requires one or more reserved core partitions, and a preserved .qdb functioning as the root partition. This design partitioning is similar to that required for the device periphery reuse or partial reconfiguration (PR) implementation flow. This tutorial includes a design example to demonstrate this setup.

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