1.2. Downloading Tutorial Design Files
- Download and extract the tutorial design files at:
- View the extracted tutorial design file directory structure.
Top-level file that instantiates iopll, big_partition1_top, blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s. Also includes logic to drive LED[4:7] as a single, shifting bit.
|top.qpf||Intel® Quartus® Prime project file that stores project name and revisions.|
|top.qsf||Intel® Quartus® Prime settings file containing project assignments and settings.|
|big_partition1_top.v||Design file that instantiates 20 instances of an OpenCores* design.|
|blinking_led_2s.sv||Logic to drive LED every two seconds.|
|blinking_led_4s.sv||Logic to drive LED every four seconds.|
|blinking_led_8s.sv||Logic to drive LED every eight seconds.|
|blinking_led_16s.sv||Logic to drive LED every 16 seconds.|
|blinking_led.sdc||A Synopsys Design Constraints file that defines the 50 MHz input reference clock.|
|iopll.ip||The IOPLL Intel® FPGA IP instantiated in top. The IP uses a 50 MHz reference clock frequency, and generates 100 MHz and 550 MHz clocks.|
|tx_dcfifo.ip||The dual clock FIFO Intel® FPGA IP instantiated in blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s instances. Has a write clock of 550 MHz and read clock of 100 MHz.|
|report_timing.tcl||A tcl script with Timing Analyzer commands to generate summary of paths reports with least positive or worst slack in each partition, and commands to report timing for two nodes in the partitions that meet timing.|
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