AN 899: Reducing Compile Time with Fast Preservation

ID 683493
Date 11/06/2019
Public

1.3.3. Step 3: View Design Assistant Results

The Intel® Quartus® Prime Design Assistant can run automatically during various stages of compilation to report any violations against a standard set of Intel FPGA-recommended design rules. You can analyze Design Assistant results to determine where you can further optimize the design. For this tutorial module, specific Hyper-Retiming Design Assistant rules are enabled in the Compiler settings.

Follow these steps to run Design Assistant:

  1. To view Design Assistant settings, click Assignments > Settings > Design Assistant Rule Settings. Design Assistant settings show that Design Assistant is enabled automatically during compilation, and that rule HRR-10101 Asynchronous Clears is enabled. HRR-10101 identifies asynchronous clear signals that prevent retiming of paths that could increase design performance.
    Figure 9. Design Assistant Settings
  2. Under the Synthesis folder of the Compilation Report, expand the Design Assistant (Elaborated) folder. Design Assistant reports that the design contains asynchronous clears that limit retiming.
    Figure 10. Design Assistant Report

    Module 2: Preserve Timing-Closed Design Partitions describes how to preserve the design partitions that don't require further optimization, allowing you to focus the Compiler's effort on areas requiring further optimization.

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