AN 899: Reducing Compile Time with Fast Preservation

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ID 683493
Date 11/06/2019
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Document Table of Contents
Document Table of Contents x
1. AN 899: Reducing Compile Time with Fast Preservation
1. AN 899: Reducing Compile Time with Fast Preservation x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Module 1: Analyze the Non-Partitioned Design 1.4. Module 2: Preserve Timing-Closed Design Partitions 1.5. Module 3: Optimize with Fast Preservation 1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History
1.3. Module 1: Analyze the Non-Partitioned Design x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: View Design Assistant Results
1.4. Module 2: Preserve Timing-Closed Design Partitions x
1.4.1. Step 1: Create Design Partitions 1.4.2. Step 2: Floorplan the Design Partitions 1.4.3. Step 3: Preserve the Timing-Closed Root Partition
1.5. Module 3: Optimize with Fast Preservation x
1.5.1. Step 1: Create a Project Revision 1.5.2. Step 2: Enable Fast Preservation 1.5.3. Step 3: Import the Root Partition 1.5.4. Step 4: Optimize the Reserved Core Partitions 1.5.5. Step 5: View Fast Preservation Results
1. AN 899: Reducing Compile Time with Fast Preservation

1.3.3. Step 3: View Design Assistant Results

The Intel® Quartus® Prime Design Assistant can run automatically during various stages of compilation to report any violations against a standard set of Intel FPGA-recommended design rules. You can analyze Design Assistant results to determine where you can further optimize the design. For this tutorial module, specific Hyper-Retiming Design Assistant rules are enabled in the Compiler settings.

Follow these steps to run Design Assistant:

  1. To view Design Assistant settings, click Assignments > Settings > Design Assistant Rule Settings. Design Assistant settings show that Design Assistant is enabled automatically during compilation, and that rule HRR-10101 Asynchronous Clears is enabled. HRR-10101 identifies asynchronous clear signals that prevent retiming of paths that could increase design performance.
    Figure 9. Design Assistant Settings
  2. Under the Synthesis folder of the Compilation Report, expand the Design Assistant (Elaborated) folder. Design Assistant reports that the design contains asynchronous clears that limit retiming.
    Figure 10. Design Assistant Report

    Module 2: Preserve Timing-Closed Design Partitions describes how to preserve the design partitions that don't require further optimization, allowing you to focus the Compiler's effort on areas requiring further optimization.

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