AN 899: Reducing Compile Time with Fast Preservation

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ID 683493
Date 11/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. AN 899: Reducing Compile Time with Fast Preservation
1. AN 899: Reducing Compile Time with Fast Preservation x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Module 1: Analyze the Non-Partitioned Design 1.4. Module 2: Preserve Timing-Closed Design Partitions 1.5. Module 3: Optimize with Fast Preservation 1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History
1.3. Module 1: Analyze the Non-Partitioned Design x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: View Design Assistant Results
1.4. Module 2: Preserve Timing-Closed Design Partitions x
1.4.1. Step 1: Create Design Partitions 1.4.2. Step 2: Floorplan the Design Partitions 1.4.3. Step 3: Preserve the Timing-Closed Root Partition
1.5. Module 3: Optimize with Fast Preservation x
1.5.1. Step 1: Create a Project Revision 1.5.2. Step 2: Enable Fast Preservation 1.5.3. Step 3: Import the Root Partition 1.5.4. Step 4: Optimize the Reserved Core Partitions 1.5.5. Step 5: View Fast Preservation Results
1. AN 899: Reducing Compile Time with Fast Preservation

1.1. Tutorial Design Overview

This tutorial includes a prepared design example to demonstrate use of fast preservation. You can download the design example to follow along with the tutorial steps in the Intel® Quartus® Prime Pro Edition software, as Downloading Tutorial Design Files describes.

The example top-level design instantiates a PLL that generates a 550 MHz fast clock (CLK1), and a 100 MHz slow clock (CLK2). The top-level design also instantiates 4 blinking LED modules that drive LED[3:0] every 2, 4, 8, and 16 seconds, respectively.

Figure 1. Incremental Block-Based Compilation Tutorial Design Example

To increase the design size in the Intel® FPGA, the design example also instantiates 20 duplicate instances of an OpenCores* design.1

The duplicate OpenCores* design instances have the following characteristics:

  • The design implements each instance in parallel.
  • I/O wrapper logic is present to reduce the number of I/O pins that the larger design requires.
  • No timing-critical paths exist between the instances and the wrapper logic.
1 Reed Solomon Decoder OpenCores* project, Varkon Semiconductors, 2010.
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