Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 12/04/2023
Public
Document Table of Contents

5.3.1. Viewing Critical Chains

Looking at the critical chain shows the exact logic that limits retiming operations in your design. For example, you can see if the retiming is limited by your RTL code, or by the constraints you applied on the design. Intel® Quartus® Prime Pro Edition reports one critical chain per clock domain and clock domain crossing.
The critical chain is available at two different stages in the Hyper Aware Design Flow:
  • In the Retiming Limit Details Report—this report for the retiming stage in the Hyper Aware Design Flow, and is enabled by default.
  • In the Fast Forward Compilation Report—Click Fast Forward Timing Closure Recommendations on the Compilation Dashboard to run..
  • You can also graphically visualize the critical chains in the Technology Map Viewer.