Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 12/04/2023
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5.8. Timing Closure and Optimization Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 23.3
  • Updated version support information and introduction of the Exploration Dashboard GUI (quartus_edw) in Aggregating and Comparing Compilation Results with Exploration Dashboard topic.
  • Revised command syntaxt in Base Exploration Dashboard Properties topic.
  • Added new property names to Project Handle Properties topic.
  • Updated Starting the Exploration Dashboard for the Exploration Dashboard GUI (quartus_edw) and options.
2023.08.01 23.2
  • Updated version support information in Aggregating and Comparing Compilation Results with Exploration Dashboard topic.
  • Corrected graphic size in Use PLLs to Shift Clock Edges.
2023.06.26 23.2
  • Revised Base Exploration Dashboard Properties topic to describe user_data property.
2023.04.03 23.1
  • Added new Aggregating and Comparing Compilation Results with Exploration Dashboard section.
  • Added new Change Adder Tree Styles topic describing new USE_COMPRESSOR_IMPLEMENTATION assignment.
  • Updated product family name to "Intel Agilex 7."
2022.01.07 21.4
  • Clarified device applicability in Spine Clock Limitations topic.
  • Added Design Assistant information to Review Timing Constraints topic.
  • Added Design Assistant information to Review Timing Constraints topic.
  • Removed references to obsolete Advisors throughout.
  • Added Design Assistant information to Optimize Source Code topic.
  • Added Design Assistant information to Improving Register-to-Register Timing topic.
  • Added Design Assistant information to Optimize Synthesis for Performance, Not Area topic.
  • Added set_clock_groups -exclusive setting information to Tips for Analyzing Failing Clock Paths that Cross Clock Domains topic.
  • Added new Register RAMS and DSPs topic.
  • Revised Metastability Analysis and Optimization Techniques topic for synchronizers.
2021.10.04 21.3
  • Updated name of Report Hierarchical Retiming Restrictions command and report to Report Retiming Restrictions.
2021.06.21 21.2
  • Added note about variables that can cause differences in the compilation results between seed sweeps with DSE II.
2020.09.28 20.3
  • Added "Back-Annotate Optimized Assignments" topic to describe new GUI support for back-annotation of pin, RAM, DSP, and clock assignments.
  • Added "Correct Design Assistant Rule Violations" topic.
  • Updated "Report Timing" topic for Extra Info tab data.
  • Added new "Report Logic Depth," "Report Neighbor Paths, "Report Register Spread," "Report Route Net of Interest," "Report Hierarchical Retiming Restrictions," and "Report Pipelining Information," topics to "Review Details of Timing Paths" section.
  • Moved "Optimize Settings with Design Space Explorer II" to "Design Evaluation for Timing Closure" section and updated links to Help.
  • Retitled "Intel Stratix 10 Timing Closure Recommendations" topic to "Implement Fast Forward Timing Closure Recommendations".
2019.07.01 19.1 Added important notes to Automatic Register Duplication: Estimated Physical Proximity and Automatic Register Duplication: Hierarchical Proximity topics.
2019.04.01 19.1
  • Added more information about register duplication methods in Duplicate Logic for Fan-out Control topic.
  • Moved content related to manual register duplication from Duplicate Logic for Fan-out Control topic to a newly created sub-topic Manually Adding Duplicate Registers.
  • Added Automatic Register Duplication: Estimated Physical Proximity and Automatic Register Duplication: Hierarchical Proximity as new sub-topics under Duplicate Logic for Fan-out Control to describe automatic register duplication process.
2018.11.12 18.1.0
  • Updated "Placement Effort Multiplier" figure and text descriptions in "Adjust Placement Effort" topic.
  • Updated "Fitter Effort" figure and text descriptions in "Adjust Fitter Effort" topic.
  • Updated "Optimize Hold Timing Option" screenshot in "Wires Added for Hold" topic.
2018.09.24 18.1.0
  • Removed duplicated topic: Resource Utilization Optimization Techniques. The topic is now in the Area Optimization chapter.
  • Removed reference to unsupported CARRY and CASCADE buffers from "Optimize IOC Register Placement for Timing Logic Option" topic.
2017.11.06 17.1.0
  • Added support for Intel® Stratix® 10 Hyper-Retiming, Fast Forward compilation, and Fast Forward Viewer.
    • Added topics: Critical Chains, Viewing Critical Chains, Intel Stratix 10 Timing Closure Recommendations, Retiming Limit Details Report, Using the Retiming Limit Details Report, Fast Forward Timing Closure Recommendations, Generating Fast Forward Timing Closure Recommendations, Implementing Fast Forward Recommendations.
  • Added topic about using partitions to achieve timing closure.
  • Moved Topic: Design Evaluation for Timing Closure after Initial Compilation: Optional Fitter Settings.
  • Removed statement about applying physical synthesis optimizations in a portion of a design.
  • Removed references to optimizing hold timing for selected paths.
  • Updated logic options about resource utilization optimization settings.
2017.05.08 17.0.0
  • Added topic: Critical Paths.
  • Updated Register-to-Register Timing and renamed to Register-to-Register Timing Analysis.
  • Renamed topic: Timing Analysis with the Timing Analyzer to Displaying Path Reports with the Timing Analyzer.
  • Removed (LUT-Based Devices) remark from topic titles.
  • Renamed topic: Optimizing Timing (LUT-Based Devices) to Timing Optimization.
  • Renamed topic: Debugging Timing Failures in the Timing Analyzer to Displaying Timing Closure Recommendations for Failing Paths.
  • Renamed topic: Improving Register-to-Register Timing Summary to Improving Register-to-Register Timing .
  • Removed topics: Tips for Locating Multiple Paths to the Chip Planner, LogicLock Assignments and Hierarchy Assignments, .
  • Removed reference to deprecated Fitter Effort Logic Option.
  • Removed information about Pin Advisor and Resource Optimization Advisor.
  • Removed figure: Clock Regions
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.02 16.0.0
  • Removed information about deprecated physical synthesis options.
  • Added information about monitoring clustering difficulty.
2015.11.02 15.1.0
  • Added: Periphery to Core Register Placement and Routing Optimization.
  • Changed instances of Quartus II to Quartus Prime.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Updated DSE II content.
June 2014 14.0.0
  • Dita conversion.
  • Removed content about obsolete devices that are no longer supported in QII software v14.0: Arria GX, Arria II, Cyclone III, Stratix II, Stratix III.
  • Replaced Megafunction content with IP core content.
November 2013 13.1.0
  • Added Design Evaluation for Timing Closure section.
  • Removed Optimizing Timing (Macrocell-Based CPLDs) section.
  • Updated Optimize Multi-Corner Timing and Fitter Aggressive Routability Optimization.
  • Updated Timing Analysis with the Timing Analyzer to show how to access the Report All Summaries command.
  • Updated Ignored Timing Constraints to include a help link to Fitter Summary Reports with the Ignored Assignment Report information.
May 2013 13.0.0
  • Renamed chapter title from Area and Timing Optimization to Timing Closure and Optimization.
  • Removed design and area/resources optimization information.
  • Added the following sections:

    Fitter Aggressive Routability Optimization.

    Tips for Analyzing Paths from/to the Source and Destination of Critical Path.

    Tips for Locating Multiple Paths to the Chip Planner.

    Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles.

November 2012 12.1.0
  • Updated “Initial Compilation: Optional Fitter Settings” on page 13–2, “I/O Assignments” on page 13–2, “Initial Compilation: Optional Fitter Settings” on page 13–2, “Resource Utilization” on page 13–9, “Routing” on page 13–21, and “Resolving Resource Utilization Problems” on page 13–43.
June 2012 12.0.0
  • Updated “Optimize Multi-Corner Timing” on page 13–6, “Resource Utilization” on page 13–10, “Timing Analysis with the Timing Analyzer” on page 13–12, “Using the Resource Optimization Advisor” on page 13–15, “Increase Placement Effort Multiplier” on page 13–22, “Increase Router Effort Multiplier” on page 13–22 and “Debugging Timing Failures in the Timing Analyzer” on page 13–24.
  • Minor text edits throughout the chapter.
November 2011 11.1.0
  • Updated the “Timing Requirement Settings”, “Standard Fit”, “Fast Fit”, “Optimize Multi-Corner Timing”, “Timing Analysis with the Timing Analyzer”, “Debugging Timing Failures in the Timing Analyzer”, “LogicLock Assignments”, “Tips for Analyzing Failing Clock Paths that Cross Clock Domains”, “Flatten the Hierarchy During Synthesis”, “Fast Input, Output, and Output Enable Registers”, and “Hierarchy Assignments” sections
  • Updated Table 13–6
  • Added the “Spine Clock Limitations” section
  • Removed the Change State Machine Encoding section from page 19
  • Removed Figure 13-5
  • Minor text edits throughout the chapter
May 2011 11.0.0
  • Reorganized sections in “Initial Compilation: Optional Fitter Settings” section
  • Added new information to “Resource Utilization” section
  • Added new information to “Duplicate Logic for Fan-Out Control” section
  • Added links to Help
  • Additional edits and updates throughout chapter
December 2010 10.1.0
  • Added links to Help
  • Updated device support
  • Added “Debugging Timing Failures in the Timing Analyzer” section
  • Removed Classic Timing Analyzer references
  • Other updates throughout chapter
August 2010 10.0.1 Corrected link
July 2010 10.0.0
  • Moved Compilation Time Optimization Techniques section to new Reducing Compilation Time chapter
  • Removed references to Timing Closure Floorplan
  • Moved Smart Compilation Setting and Early Timing Estimation sections to new Reducing Compilation Time chapter
  • Added Other Optimization Resources section
  • Removed outdated information
  • Changed references to DSE chapter to Help links
  • Linked to Help where appropriate
  • Removed Referenced Documents section